EDN Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: `8b2da8db5e`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.050s	31.064us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.940s	15.881us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.000s	17.910us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.330s	181.346us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.210s	29.345us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.860s	26.461us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.000s	17.910us	20	20	100.00
		edn_csr_aliasing	1.210s	29.345us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.166m	2.307ms	300	300	100.00
V2	csrng_commands	edn_genbits	1.166m	2.307ms	300	300	100.00
V2	genbits	edn_genbits	1.166m	2.307ms	300	300	100.00
V2	interrupts	edn_intr	1.230s	21.341us	50	50	100.00
V2	alerts	edn_alert	1.450s	248.811us	200	200	100.00
V2	errs	edn_err	1.400s	34.304us	100	100	100.00
V2	disable	edn_disable	0.920s	14.650us	50	50	100.00
		edn_disable_auto_req_mode	1.570s	55.951us	50	50	100.00
V2	stress_all	edn_stress_all	5.940s	301.288us	50	50	100.00
V2	intr_test	edn_intr_test	0.960s	15.270us	50	50	100.00
V2	alert_test	edn_alert_test	1.110s	27.725us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.280s	116.734us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.280s	116.734us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.940s	15.881us	5	5	100.00
		edn_csr_rw	1.000s	17.910us	20	20	100.00
		edn_csr_aliasing	1.210s	29.345us	5	5	100.00
		edn_same_csr_outstanding	1.560s	139.407us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.940s	15.881us	5	5	100.00
		edn_csr_rw	1.000s	17.910us	20	20	100.00
		edn_csr_aliasing	1.210s	29.345us	5	5	100.00
		edn_same_csr_outstanding	1.560s	139.407us	20	20	100.00
V2		TOTAL			940	940	100.00
V2S	tl_intg_err	edn_sec_cm	8.510s	2.261ms	5	5	100.00
		edn_tl_intg_err	5.110s	1.017ms	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.990s	20.288us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.450s	248.811us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	8.510s	2.261ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	8.510s	2.261ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	8.510s	2.261ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	8.510s	2.261ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.450s	248.811us	200	200	100.00
		edn_sec_cm	8.510s	2.261ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.450s	248.811us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	5.110s	1.017ms	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	42.314m	574.480ms	49	50	98.00
V3		TOTAL			49	50	98.00
		TOTAL			1129	1130	99.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.61	98.25	93.91	97.02	91.86	96.37	99.77	92.08

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:758) [edn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test edn_stress_all_with_rand_reset has 1 failures.
  - 24.edn_stress_all_with_rand_reset.50563326940545166483863655178702599362818443951904936860757131533943640043483
    Line 343, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/24.edn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 3899745182 ps: (cip_base_vseq.sv:758) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 3899745182 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

EDN Simulation Results

Wednesday July 17 2024 23:02:16 UTC

GitHub Revision: 8b2da8db5e

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 31877364624131593519988921539075110140045739991215723614576185349550879231344

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `8b2da8db5e`