EDN Simulation Results

Thursday July 18 2024 23:02:12 UTC

GitHub Revision: 974aaab627

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 46057207235241274571178436692064798722168129065126426307050395083305588858879

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.050s 17.893us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.960s 16.602us 5 5 100.00
V1 csr_rw edn_csr_rw 0.960s 17.303us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 5.130s 176.570us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.480s 153.037us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.810s 80.721us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.960s 17.303us 20 20 100.00
edn_csr_aliasing 1.480s 153.037us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.321m 2.489ms 300 300 100.00
V2 csrng_commands edn_genbits 1.321m 2.489ms 300 300 100.00
V2 genbits edn_genbits 1.321m 2.489ms 300 300 100.00
V2 interrupts edn_intr 1.190s 23.530us 50 50 100.00
V2 alerts edn_alert 1.490s 289.120us 200 200 100.00
V2 errs edn_err 1.390s 30.045us 100 100 100.00
V2 disable edn_disable 1.000s 13.537us 50 50 100.00
edn_disable_auto_req_mode 1.490s 42.387us 50 50 100.00
V2 stress_all edn_stress_all 8.390s 473.174us 50 50 100.00
V2 intr_test edn_intr_test 1.040s 204.725us 50 50 100.00
V2 alert_test edn_alert_test 1.290s 40.105us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.500s 540.834us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.500s 540.834us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.960s 16.602us 5 5 100.00
edn_csr_rw 0.960s 17.303us 20 20 100.00
edn_csr_aliasing 1.480s 153.037us 5 5 100.00
edn_same_csr_outstanding 1.510s 257.498us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.960s 16.602us 5 5 100.00
edn_csr_rw 0.960s 17.303us 20 20 100.00
edn_csr_aliasing 1.480s 153.037us 5 5 100.00
edn_same_csr_outstanding 1.510s 257.498us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 14.710s 1.037ms 5 5 100.00
edn_tl_intg_err 2.880s 113.929us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.080s 15.000us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.490s 289.120us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 14.710s 1.037ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 14.710s 1.037ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 14.710s 1.037ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 14.710s 1.037ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.490s 289.120us 200 200 100.00
edn_sec_cm 14.710s 1.037ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.490s 289.120us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.880s 113.929us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 45.909m 401.538ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.36 98.25 93.91 97.02 90.12 96.37 99.77 92.08

Past Results