EDN Simulation Results

Friday July 19 2024 23:02:26 UTC

GitHub Revision: e971cd9798

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26138077499038500271813583950138268511494909685260487774440110801232111361107

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.090s 21.142us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.020s 23.603us 5 5 100.00
V1 csr_rw edn_csr_rw 0.950s 14.877us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.730s 2.088ms 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.520s 34.559us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.530s 78.522us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.950s 14.877us 20 20 100.00
edn_csr_aliasing 1.520s 34.559us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.138m 2.220ms 300 300 100.00
V2 csrng_commands edn_genbits 1.138m 2.220ms 300 300 100.00
V2 genbits edn_genbits 1.138m 2.220ms 300 300 100.00
V2 interrupts edn_intr 1.220s 21.284us 50 50 100.00
V2 alerts edn_alert 1.650s 416.125us 200 200 100.00
V2 errs edn_err 1.640s 54.162us 100 100 100.00
V2 disable edn_disable 0.980s 11.568us 50 50 100.00
edn_disable_auto_req_mode 1.380s 488.223us 50 50 100.00
V2 stress_all edn_stress_all 7.810s 428.607us 50 50 100.00
V2 intr_test edn_intr_test 1.000s 15.714us 50 50 100.00
V2 alert_test edn_alert_test 1.830s 73.257us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.640s 623.538us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.640s 623.538us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.020s 23.603us 5 5 100.00
edn_csr_rw 0.950s 14.877us 20 20 100.00
edn_csr_aliasing 1.520s 34.559us 5 5 100.00
edn_same_csr_outstanding 1.570s 388.905us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.020s 23.603us 5 5 100.00
edn_csr_rw 0.950s 14.877us 20 20 100.00
edn_csr_aliasing 1.520s 34.559us 5 5 100.00
edn_same_csr_outstanding 1.570s 388.905us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 9.440s 618.953us 5 5 100.00
edn_tl_intg_err 2.790s 121.340us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.020s 56.733us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.650s 416.125us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 9.440s 618.953us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 9.440s 618.953us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 9.440s 618.953us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 9.440s 618.953us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.650s 416.125us 200 200 100.00
edn_sec_cm 9.440s 618.953us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.650s 416.125us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.790s 121.340us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 39.327m 368.970ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 1130 1130 100.00

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.53 98.25 93.97 97.02 91.28 96.37 99.77 92.08

Past Results