EDN Simulation Results

Tuesday August 13 2024 23:04:47 UTC

GitHub Revision: 098010d125

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 12185085088694708177096441863424670920996379189869351644310607217057882846251

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.070s 17.892us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.980s 34.063us 5 5 100.00
V1 csr_rw edn_csr_rw 0.970s 16.207us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 4.970s 830.627us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.540s 99.534us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.670s 27.525us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.970s 16.207us 20 20 100.00
edn_csr_aliasing 1.540s 99.534us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 2.018m 8.793ms 300 300 100.00
V2 csrng_commands edn_genbits 2.018m 8.793ms 300 300 100.00
V2 genbits edn_genbits 2.018m 8.793ms 300 300 100.00
V2 interrupts edn_intr 1.230s 22.023us 50 50 100.00
V2 alerts edn_alert 1.450s 280.427us 200 200 100.00
V2 errs edn_err 1.470s 29.596us 100 100 100.00
V2 disable edn_disable 1.000s 14.118us 50 50 100.00
edn_disable_auto_req_mode 1.570s 35.441us 50 50 100.00
V2 stress_all edn_stress_all 6.580s 332.041us 50 50 100.00
V2 intr_test edn_intr_test 0.990s 17.750us 50 50 100.00
V2 alert_test edn_alert_test 1.090s 20.412us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.610s 621.401us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.610s 621.401us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.980s 34.063us 5 5 100.00
edn_csr_rw 0.970s 16.207us 20 20 100.00
edn_csr_aliasing 1.540s 99.534us 5 5 100.00
edn_same_csr_outstanding 1.550s 43.182us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.980s 34.063us 5 5 100.00
edn_csr_rw 0.970s 16.207us 20 20 100.00
edn_csr_aliasing 1.540s 99.534us 5 5 100.00
edn_same_csr_outstanding 1.550s 43.182us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 10.380s 2.248ms 5 5 100.00
edn_tl_intg_err 5.430s 291.595us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.020s 18.598us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.450s 280.427us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 10.380s 2.248ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 10.380s 2.248ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 10.380s 2.248ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 10.380s 2.248ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.450s 280.427us 200 200 100.00
edn_sec_cm 10.380s 2.248ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.450s 280.427us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 5.430s 291.595us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 2.372m 20.837ms 31 50 62.00
V3 TOTAL 31 50 62.00
TOTAL 1111 1130 98.32

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.68 98.25 93.91 97.02 91.28 96.37 99.77 93.18

Failure Buckets

Past Results