EDN Simulation Results

Wednesday August 14 2024 23:02:33 UTC

GitHub Revision: 584c3d46af

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 75916000169703078066460267353397937307391759551032957123310220571514951708138

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.070s 18.316us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.000s 32.968us 5 5 100.00
V1 csr_rw edn_csr_rw 0.960s 14.579us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.390s 508.936us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.240s 26.530us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.650s 41.411us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.960s 14.579us 20 20 100.00
edn_csr_aliasing 1.240s 26.530us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 2.005m 9.061ms 300 300 100.00
V2 csrng_commands edn_genbits 2.005m 9.061ms 300 300 100.00
V2 genbits edn_genbits 2.005m 9.061ms 300 300 100.00
V2 interrupts edn_intr 1.170s 20.428us 50 50 100.00
V2 alerts edn_alert 1.410s 31.446us 200 200 100.00
V2 errs edn_err 1.360s 26.990us 100 100 100.00
V2 disable edn_disable 1.000s 15.422us 50 50 100.00
edn_disable_auto_req_mode 1.650s 62.120us 50 50 100.00
V2 stress_all edn_stress_all 7.390s 368.235us 50 50 100.00
V2 intr_test edn_intr_test 0.980s 15.977us 50 50 100.00
V2 alert_test edn_alert_test 1.140s 41.047us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.480s 2.299ms 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.480s 2.299ms 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.000s 32.968us 5 5 100.00
edn_csr_rw 0.960s 14.579us 20 20 100.00
edn_csr_aliasing 1.240s 26.530us 5 5 100.00
edn_same_csr_outstanding 1.450s 128.459us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.000s 32.968us 5 5 100.00
edn_csr_rw 0.960s 14.579us 20 20 100.00
edn_csr_aliasing 1.240s 26.530us 5 5 100.00
edn_same_csr_outstanding 1.450s 128.459us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 9.520s 1.581ms 5 5 100.00
edn_tl_intg_err 4.450s 668.069us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.030s 18.284us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.410s 31.446us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 9.520s 1.581ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 9.520s 1.581ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 9.520s 1.581ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 9.520s 1.581ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.410s 31.446us 200 200 100.00
edn_sec_cm 9.520s 1.581ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.410s 31.446us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 4.450s 668.069us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 2.054m 4.526ms 35 50 70.00
V3 TOTAL 35 50 70.00
TOTAL 1115 1130 98.67

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.86 98.25 93.97 97.02 92.44 96.37 99.77 93.18

Failure Buckets

Past Results