EDN Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: `d09e282b26`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.090s	17.447us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.950s	28.532us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.990s	18.933us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.010s	173.857us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.190s	88.133us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.910s	103.530us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.990s	18.933us	20	20	100.00
		edn_csr_aliasing	1.190s	88.133us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	3.950s	276.916us	300	300	100.00
V2	csrng_commands	edn_genbits	3.950s	276.916us	300	300	100.00
V2	genbits	edn_genbits	3.950s	276.916us	300	300	100.00
V2	interrupts	edn_intr	1.240s	20.800us	50	50	100.00
V2	alerts	edn_alert	1.460s	359.207us	200	200	100.00
V2	errs	edn_err	1.420s	27.646us	100	100	100.00
V2	disable	edn_disable	0.970s	16.938us	50	50	100.00
		edn_disable_auto_req_mode	1.590s	43.692us	49	50	98.00
V2	stress_all	edn_stress_all	6.920s	351.775us	50	50	100.00
V2	intr_test	edn_intr_test	0.960s	81.248us	50	50	100.00
V2	alert_test	edn_alert_test	1.520s	55.476us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	4.020s	110.065us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	4.020s	110.065us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.950s	28.532us	5	5	100.00
		edn_csr_rw	0.990s	18.933us	20	20	100.00
		edn_csr_aliasing	1.190s	88.133us	5	5	100.00
		edn_same_csr_outstanding	1.600s	54.131us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.950s	28.532us	5	5	100.00
		edn_csr_rw	0.990s	18.933us	20	20	100.00
		edn_csr_aliasing	1.190s	88.133us	5	5	100.00
		edn_same_csr_outstanding	1.600s	54.131us	20	20	100.00
V2		TOTAL			939	940	99.89
V2S	tl_intg_err	edn_sec_cm	11.760s	738.963us	5	5	100.00
		edn_tl_intg_err	4.130s	203.610us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.080s	18.255us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.460s	359.207us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	11.760s	738.963us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	11.760s	738.963us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	11.760s	738.963us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	11.760s	738.963us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.460s	359.207us	200	200	100.00
		edn_sec_cm	11.760s	738.963us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.460s	359.207us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	4.130s	203.610us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	2.747h	10.000s	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			1106	1130	97.88

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.72	98.25	93.97	97.02	91.86	96.37	99.77	92.80

Failure Buckets

Job edn-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 19 failures:
- Test edn_stress_all_with_rand_reset has 19 failures.
  - 0.edn_stress_all_with_rand_reset.65194316538043526796053303524271455682310926438015053850711331395730257513426
    Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:f79ba0b9-a693-49bd-a0bb-2726e3b34d92
```
  - 5.edn_stress_all_with_rand_reset.16310096373508901836989985154070343133361829406552057537173451422630779443456
    Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/5.edn_stress_all_with_rand_reset/latest/run.log
```
  Job ID: smart:65ade72a-6b28-476c-b425-43c4830bb62a
```
  - ... and 17 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test edn_stress_all_with_rand_reset has 2 failures.
  - 38.edn_stress_all_with_rand_reset.71368415980537001649364844516506515450516592257672477949512782590817197834848
    Line 593, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/38.edn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.edn_stress_all_with_rand_reset.19802830264415101001088669124369859864843819561657693501304808852515163355206
    Line 537, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/40.edn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:771) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test edn_stress_all_with_rand_reset has 1 failures.
  - 31.edn_stress_all_with_rand_reset.11190832395468715115790480826176194803107523085979678243018285394197100461801
    Line 382, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/31.edn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 1639683604 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @ 1639683604 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_endpoint_pull_seq[*]' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
- Test edn_stress_all_with_rand_reset has 1 failures.
  - 36.edn_stress_all_with_rand_reset.110333990328127446033735799721190801766904269525265408655580116647766002481039
    Line 305, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/36.edn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  88896947 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_endpoint_agent[0].sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_endpoint_agent[0].sequencer' for sequence 'uvm_test_top.env.m_endpoint_agent[0].sequencer.m_endpoint_pull_seq[0]' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
  UVM_INFO @  88896947 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (edn_scoreboard.sv:579) [scoreboard] Check failed (reqs_between_reseeds_ctr < max_num_reqs_between_reseeds) Maximum number of request between reseeds in auto_req_mode * exceeded. has 1 failures:
- Test edn_disable_auto_req_mode has 1 failures.
  - 49.edn_disable_auto_req_mode.105040317470347267416992569770130923993621186262247234656662085974238724846962
    Line 264, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/49.edn_disable_auto_req_mode/latest/run.log
```
  UVM_FATAL @  94170532 ps: (edn_scoreboard.sv:579) [uvm_test_top.env.scoreboard] Check failed (reqs_between_reseeds_ctr < max_num_reqs_between_reseeds) Maximum number of request between reseeds in auto_req_mode 0x00000001 exceeded.
  UVM_INFO @  94170532 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

EDN Simulation Results

Thursday August 15 2024 23:02:21 UTC

GitHub Revision: d09e282b26

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 47908880312501934977153450267828796412449789719488445881682136509150457490963

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `d09e282b26`