EDN Simulation Results

Friday August 16 2024 23:02:10 UTC

GitHub Revision: 76588857da

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 107397868712693014844033025164446565408841343499325418676943424680076749785789

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.080s 18.822us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.940s 33.547us 5 5 100.00
V1 csr_rw edn_csr_rw 0.960s 23.322us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.640s 586.801us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.580s 80.271us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.020s 438.930us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.960s 23.322us 20 20 100.00
edn_csr_aliasing 1.580s 80.271us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 9.010s 1.186ms 300 300 100.00
V2 csrng_commands edn_genbits 9.010s 1.186ms 300 300 100.00
V2 genbits edn_genbits 9.010s 1.186ms 300 300 100.00
V2 interrupts edn_intr 1.290s 22.303us 50 50 100.00
V2 alerts edn_alert 1.480s 40.618us 200 200 100.00
V2 errs edn_err 1.470s 34.331us 100 100 100.00
V2 disable edn_disable 0.950s 39.588us 50 50 100.00
edn_disable_auto_req_mode 1.450s 31.695us 50 50 100.00
V2 stress_all edn_stress_all 8.340s 553.543us 50 50 100.00
V2 intr_test edn_intr_test 0.990s 16.437us 50 50 100.00
V2 alert_test edn_alert_test 1.390s 43.133us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.190s 911.069us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.190s 911.069us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.940s 33.547us 5 5 100.00
edn_csr_rw 0.960s 23.322us 20 20 100.00
edn_csr_aliasing 1.580s 80.271us 5 5 100.00
edn_same_csr_outstanding 1.460s 392.282us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.940s 33.547us 5 5 100.00
edn_csr_rw 0.960s 23.322us 20 20 100.00
edn_csr_aliasing 1.580s 80.271us 5 5 100.00
edn_same_csr_outstanding 1.460s 392.282us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 9.350s 1.049ms 5 5 100.00
edn_tl_intg_err 3.100s 339.595us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.080s 19.529us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.480s 40.618us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 9.350s 1.049ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 9.350s 1.049ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 9.350s 1.049ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 9.350s 1.049ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.480s 40.618us 200 200 100.00
edn_sec_cm 9.350s 1.049ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.480s 40.618us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.100s 339.595us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 2.827h 10.000s 31 50 62.00
V3 TOTAL 31 50 62.00
TOTAL 1111 1130 98.32

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.72 98.25 93.97 97.02 91.28 96.37 99.77 93.37

Failure Buckets

Past Results