76588857da| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | edn_smoke | 1.070s | 18.140us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | edn_csr_hw_reset | 0.950s | 28.478us | 5 | 5 | 100.00 |
| V1 | csr_rw | edn_csr_rw | 1.000s | 16.264us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | edn_csr_bit_bash | 6.110s | 471.397us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | edn_csr_aliasing | 1.620s | 37.703us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | edn_csr_mem_rw_with_rand_reset | 2.060s | 340.819us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | edn_csr_rw | 1.000s | 16.264us | 20 | 20 | 100.00 |
| edn_csr_aliasing | 1.620s | 37.703us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | firmware | edn_genbits | 1.472m | 4.369ms | 300 | 300 | 100.00 |
| V2 | csrng_commands | edn_genbits | 1.472m | 4.369ms | 300 | 300 | 100.00 |
| V2 | genbits | edn_genbits | 1.472m | 4.369ms | 300 | 300 | 100.00 |
| V2 | interrupts | edn_intr | 1.200s | 20.335us | 50 | 50 | 100.00 |
| V2 | alerts | edn_alert | 1.550s | 391.746us | 200 | 200 | 100.00 |
| V2 | errs | edn_err | 1.340s | 28.545us | 100 | 100 | 100.00 |
| V2 | disable | edn_disable | 1.050s | 13.512us | 50 | 50 | 100.00 |
| edn_disable_auto_req_mode | 1.560s | 51.843us | 50 | 50 | 100.00 | ||
| V2 | stress_all | edn_stress_all | 7.270s | 398.819us | 50 | 50 | 100.00 |
| V2 | intr_test | edn_intr_test | 0.970s | 14.562us | 50 | 50 | 100.00 |
| V2 | alert_test | edn_alert_test | 1.230s | 35.799us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | edn_tl_errors | 4.880s | 150.993us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | edn_tl_errors | 4.880s | 150.993us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | edn_csr_hw_reset | 0.950s | 28.478us | 5 | 5 | 100.00 |
| edn_csr_rw | 1.000s | 16.264us | 20 | 20 | 100.00 | ||
| edn_csr_aliasing | 1.620s | 37.703us | 5 | 5 | 100.00 | ||
| edn_same_csr_outstanding | 1.410s | 126.723us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | edn_csr_hw_reset | 0.950s | 28.478us | 5 | 5 | 100.00 |
| edn_csr_rw | 1.000s | 16.264us | 20 | 20 | 100.00 | ||
| edn_csr_aliasing | 1.620s | 37.703us | 5 | 5 | 100.00 | ||
| edn_same_csr_outstanding | 1.410s | 126.723us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 940 | 940 | 100.00 | |||
| V2S | tl_intg_err | edn_sec_cm | 11.320s | 731.392us | 5 | 5 | 100.00 |
| edn_tl_intg_err | 3.240s | 142.291us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_regwen | edn_regwen | 1.050s | 20.384us | 10 | 10 | 100.00 |
| V2S | sec_cm_config_mubi | edn_alert | 1.550s | 391.746us | 200 | 200 | 100.00 |
| V2S | sec_cm_main_sm_fsm_sparse | edn_sec_cm | 11.320s | 731.392us | 5 | 5 | 100.00 |
| V2S | sec_cm_ack_sm_fsm_sparse | edn_sec_cm | 11.320s | 731.392us | 5 | 5 | 100.00 |
| V2S | sec_cm_fifo_ctr_redun | edn_sec_cm | 11.320s | 731.392us | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | edn_sec_cm | 11.320s | 731.392us | 5 | 5 | 100.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | edn_alert | 1.550s | 391.746us | 200 | 200 | 100.00 |
| edn_sec_cm | 11.320s | 731.392us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_cs_rdata_bus_consistency | edn_alert | 1.550s | 391.746us | 200 | 200 | 100.00 |
| V2S | sec_cm_tile_link_bus_integrity | edn_tl_intg_err | 3.240s | 142.291us | 20 | 20 | 100.00 |
| V2S | TOTAL | 35 | 35 | 100.00 | |||
| V3 | stress_all_with_rand_reset | edn_stress_all_with_rand_reset | 1.685m | 3.742ms | 31 | 50 | 62.00 |
| V3 | TOTAL | 31 | 50 | 62.00 | |||
| TOTAL | 1111 | 1130 | 98.32 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 11 | 11 | 11 | 100.00 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 95.69 | 98.25 | 93.97 | 97.02 | 91.28 | 96.37 | 99.77 | 93.18 |
Job edn-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 18 failures:
0.edn_stress_all_with_rand_reset.59394914159229238426437501336933578041757499462416445981865322297395151893520
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log
Job ID: smart:f6002c8f-1bcc-4db3-9052-69b9b9ba2245
1.edn_stress_all_with_rand_reset.16162826572735169359698877893534698986869654783731246781768596318957681272612
Log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest/run.log
Job ID: smart:5ddc852a-4963-4c75-888d-8d040b42352f
... and 16 more failures.
UVM_ERROR (cip_base_vseq.sv:771) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
8.edn_stress_all_with_rand_reset.30182734766005453532755343830467295763811878997053931995030448289975885670944
Line 339, in log /container/opentitan-public/scratch/os_regression/edn-sim-vcs/8.edn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 1530424551 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
UVM_INFO @ 1530424551 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---