EDN Simulation Results

Sunday August 18 2024 23:02:23 UTC

GitHub Revision: f1535c5540

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29514139809134543525249635699831421949407409612590789671953066019961489233719

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.090s 78.926us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 0.980s 16.590us 5 5 100.00
V1 csr_rw edn_csr_rw 0.960s 19.407us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.380s 263.772us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.660s 45.963us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.860s 31.501us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 0.960s 19.407us 20 20 100.00
edn_csr_aliasing 1.660s 45.963us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 4.370s 657.430us 300 300 100.00
V2 csrng_commands edn_genbits 4.370s 657.430us 300 300 100.00
V2 genbits edn_genbits 4.370s 657.430us 300 300 100.00
V2 interrupts edn_intr 1.250s 21.325us 50 50 100.00
V2 alerts edn_alert 1.450s 356.544us 200 200 100.00
V2 errs edn_err 1.360s 29.862us 100 100 100.00
V2 disable edn_disable 1.000s 18.149us 50 50 100.00
edn_disable_auto_req_mode 1.560s 49.814us 50 50 100.00
V2 stress_all edn_stress_all 6.230s 516.564us 50 50 100.00
V2 intr_test edn_intr_test 0.960s 16.675us 50 50 100.00
V2 alert_test edn_alert_test 1.190s 107.016us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.160s 241.292us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.160s 241.292us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 0.980s 16.590us 5 5 100.00
edn_csr_rw 0.960s 19.407us 20 20 100.00
edn_csr_aliasing 1.660s 45.963us 5 5 100.00
edn_same_csr_outstanding 1.500s 38.690us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 0.980s 16.590us 5 5 100.00
edn_csr_rw 0.960s 19.407us 20 20 100.00
edn_csr_aliasing 1.660s 45.963us 5 5 100.00
edn_same_csr_outstanding 1.500s 38.690us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 9.560s 1.880ms 5 5 100.00
edn_tl_intg_err 16.230s 1.038ms 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.060s 16.279us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.450s 356.544us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 9.560s 1.880ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 9.560s 1.880ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 9.560s 1.880ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 9.560s 1.880ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.450s 356.544us 200 200 100.00
edn_sec_cm 9.560s 1.880ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.450s 356.544us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 16.230s 1.038ms 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 2.957h 10.000s 28 50 56.00
V3 TOTAL 28 50 56.00
TOTAL 1108 1130 98.05

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.83 98.25 93.97 97.02 92.44 96.37 99.77 92.99

Failure Buckets

Past Results