EDN Simulation Results

Monday August 19 2024 23:02:17 UTC

GitHub Revision: e45ccd274a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28901767565311589526059483176077826609560752276120463932311122284088110669824

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.050s 18.530us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.020s 20.064us 5 5 100.00
V1 csr_rw edn_csr_rw 1.010s 16.868us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 6.390s 2.139ms 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.560s 37.142us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 1.740s 101.845us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.010s 16.868us 20 20 100.00
edn_csr_aliasing 1.560s 37.142us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 5.120s 468.503us 300 300 100.00
V2 csrng_commands edn_genbits 5.120s 468.503us 300 300 100.00
V2 genbits edn_genbits 5.120s 468.503us 300 300 100.00
V2 interrupts edn_intr 1.190s 23.218us 50 50 100.00
V2 alerts edn_alert 1.390s 29.885us 200 200 100.00
V2 errs edn_err 1.460s 37.212us 100 100 100.00
V2 disable edn_disable 0.980s 14.452us 50 50 100.00
edn_disable_auto_req_mode 1.580s 54.689us 50 50 100.00
V2 stress_all edn_stress_all 6.070s 588.745us 50 50 100.00
V2 intr_test edn_intr_test 0.990s 16.545us 50 50 100.00
V2 alert_test edn_alert_test 1.130s 22.710us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 3.890s 103.343us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 3.890s 103.343us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.020s 20.064us 5 5 100.00
edn_csr_rw 1.010s 16.868us 20 20 100.00
edn_csr_aliasing 1.560s 37.142us 5 5 100.00
edn_same_csr_outstanding 1.580s 38.944us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.020s 20.064us 5 5 100.00
edn_csr_rw 1.010s 16.868us 20 20 100.00
edn_csr_aliasing 1.560s 37.142us 5 5 100.00
edn_same_csr_outstanding 1.580s 38.944us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 10.720s 652.994us 5 5 100.00
edn_tl_intg_err 2.890s 128.560us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.010s 18.954us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 1.390s 29.885us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 10.720s 652.994us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 10.720s 652.994us 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 10.720s 652.994us 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 10.720s 652.994us 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 1.390s 29.885us 200 200 100.00
edn_sec_cm 10.720s 652.994us 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 1.390s 29.885us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 2.890s 128.560us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 2.218m 9.808ms 38 50 76.00
V3 TOTAL 38 50 76.00
TOTAL 1118 1130 98.94

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.77 98.25 93.91 97.02 91.86 96.37 99.77 93.18

Failure Buckets

Past Results