EDN Simulation Results

Wednesday August 21 2024 01:12:47 UTC

GitHub Revision: `34b8fc33e3`

Branch: earlgrey_1_0_0_2024_08_20_RC0

Simulator: VCS

Build randomization enabled with --build-seed 77645589415139663032322841827996135987237190720163469870959218015679941996572

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	1.550s	19.306us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	1.450s	18.476us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.410s	16.662us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	8.390s	219.548us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	2.200s	39.143us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.590s	30.899us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.410s	16.662us	20	20	100.00
		edn_csr_aliasing	2.200s	39.143us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	1.321m	4.460ms	297	300	99.00
V2	csrng_commands	edn_genbits	1.321m	4.460ms	297	300	99.00
V2	genbits	edn_genbits	1.321m	4.460ms	297	300	99.00
V2	interrupts	edn_intr	1.780s	22.786us	50	50	100.00
V2	alerts	edn_alert	2.160s	272.499us	200	200	100.00
V2	errs	edn_err	2.020s	26.522us	100	100	100.00
V2	disable	edn_disable	1.400s	13.163us	50	50	100.00
		edn_disable_auto_req_mode	2.400s	60.227us	50	50	100.00
V2	stress_all	edn_stress_all	9.850s	418.813us	50	50	100.00
V2	intr_test	edn_intr_test	1.480s	260.206us	50	50	100.00
V2	alert_test	edn_alert_test	2.560s	160.368us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	6.060s	257.430us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	6.060s	257.430us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.450s	18.476us	5	5	100.00
		edn_csr_rw	1.410s	16.662us	20	20	100.00
		edn_csr_aliasing	2.200s	39.143us	5	5	100.00
		edn_same_csr_outstanding	2.050s	132.405us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.450s	18.476us	5	5	100.00
		edn_csr_rw	1.410s	16.662us	20	20	100.00
		edn_csr_aliasing	2.200s	39.143us	5	5	100.00
		edn_same_csr_outstanding	2.050s	132.405us	20	20	100.00
V2		TOTAL			937	940	99.68
V2S	tl_intg_err	edn_sec_cm	12.330s	1.429ms	5	5	100.00
		edn_tl_intg_err	4.330s	158.854us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.380s	19.311us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	2.160s	272.499us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	12.330s	1.429ms	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	12.330s	1.429ms	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	12.330s	1.429ms	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	12.330s	1.429ms	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	2.160s	272.499us	200	200	100.00
		edn_sec_cm	12.330s	1.429ms	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	2.160s	272.499us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	4.330s	158.854us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	2.572m	21.779ms	34	50	68.00
V3		TOTAL			34	50	68.00
		TOTAL			1111	1130	98.32

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.99	98.25	93.97	97.02	93.02	96.37	99.77	93.56

Failure Buckets

Job timed out after * minutes has 16 failures:
- Test edn_stress_all_with_rand_reset has 16 failures.
  - 4.edn_stress_all_with_rand_reset.37377461144970261747160413884388670821257496951129531521221814089718031102258
    Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/4.edn_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 180 minutes
```
  - 6.edn_stress_all_with_rand_reset.32862286132797425947684460560967232474761545486205073896958537492149821088190
    Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/6.edn_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 180 minutes
```
  - ... and 14 more failures.

Job returned non-zero exit code has 3 failures:

Test edn_genbits has 3 failures.

200.edn_genbits.109431463783279150942834496196515120658103551956680350559998379637442454175204
Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/200.edn_genbits/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Aug 21 08:53 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/lowrisc/opentitan/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

201.edn_genbits.34205046093234885173556042107334627225655976774010963738333272883207816812276
Log /workspaces/lowrisc/opentitan/scratch/earlgrey_1_0_0_2024_08_20_RC0/edn-sim-vcs/201.edn_genbits/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Aug 21 08:53 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/lowrisc/opentitan/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

... and 1 more failures.