EDN Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: `0825c81be0`

Branch: os_regression_2024_08_22

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	0.990s	125.878us	50	50	100.00
V1	csr_hw_reset	edn_csr_hw_reset	0.780s	15.502us	5	5	100.00
V1	csr_rw	edn_csr_rw	0.810s	14.753us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	5.390s	1.001ms	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	1.150s	298.291us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	1.670s	28.939us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	0.810s	14.753us	20	20	100.00
		edn_csr_aliasing	1.150s	298.291us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	firmware	edn_genbits	3.780s	718.599us	300	300	100.00
V2	csrng_commands	edn_genbits	3.780s	718.599us	300	300	100.00
V2	genbits	edn_genbits	3.780s	718.599us	300	300	100.00
V2	interrupts	edn_intr	0.970s	21.977us	50	50	100.00
V2	alerts	edn_alert	1.290s	105.952us	200	200	100.00
V2	errs	edn_err	1.150s	36.086us	100	100	100.00
V2	disable	edn_disable	0.860s	12.404us	50	50	100.00
		edn_disable_auto_req_mode	1.450s	46.371us	50	50	100.00
V2	stress_all	edn_stress_all	6.010s	4.723ms	50	50	100.00
V2	intr_test	edn_intr_test	0.810s	14.065us	50	50	100.00
V2	alert_test	edn_alert_test	1.330s	58.559us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	3.820s	2.128ms	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	3.820s	2.128ms	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	0.780s	15.502us	5	5	100.00
		edn_csr_rw	0.810s	14.753us	20	20	100.00
		edn_csr_aliasing	1.150s	298.291us	5	5	100.00
		edn_same_csr_outstanding	1.280s	73.899us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	0.780s	15.502us	5	5	100.00
		edn_csr_rw	0.810s	14.753us	20	20	100.00
		edn_csr_aliasing	1.150s	298.291us	5	5	100.00
		edn_same_csr_outstanding	1.280s	73.899us	20	20	100.00
V2		TOTAL			940	940	100.00
V2S	tl_intg_err	edn_sec_cm	6.900s	500.108us	5	5	100.00
		edn_tl_intg_err	3.180s	187.403us	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	0.890s	22.546us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	1.290s	105.952us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	6.900s	500.108us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	6.900s	500.108us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	6.900s	500.108us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	6.900s	500.108us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	1.290s	105.952us	200	200	100.00
		edn_sec_cm	6.900s	500.108us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	1.290s	105.952us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	3.180s	187.403us	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	2.567h	10.000s	37	50	74.00
V3		TOTAL			37	50	74.00
		TOTAL			1117	1130	98.85

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	11	11	11	100.00
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.63	98.25	93.91	97.02	91.28	96.37	99.77	92.80

Failure Buckets

Job timed out after * minutes has 10 failures:
- Test edn_stress_all_with_rand_reset has 10 failures.
  - 0.edn_stress_all_with_rand_reset.17366083139549397455170518058751167417792648264967116265710421971580419900256
    Log /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/0.edn_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 180 minutes
```
  - 6.edn_stress_all_with_rand_reset.899675002327565016830460971450212775340557848148481426586698531675821261006
    Log /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/6.edn_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 180 minutes
```
  - ... and 8 more failures.
UVM_FATAL (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of * ps hit, indicating a probable testbench issue has 2 failures:
- Test edn_stress_all_with_rand_reset has 2 failures.
  - 30.edn_stress_all_with_rand_reset.69095921470378635443175501886925094440786910995411007858408213810416370413066
    Line 232, in log /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/30.edn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 43.edn_stress_all_with_rand_reset.96775505076396064965670147835347402858578333124524338393454602646963703373064
    Line 447, in log /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/43.edn_stress_all_with_rand_reset/latest/run.log
```
  UVM_FATAL @ 10000000000000 ps: (uvm_phase.svh:1512) [PH_TIMEOUT] Explicit timeout of 10000000000000 ps hit, indicating a probable testbench issue
  UVM_INFO @ 10000000000000 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_vseq.sv:771) [edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
- Test edn_stress_all_with_rand_reset has 1 failures.
  - 49.edn_stress_all_with_rand_reset.103794994472104669072808962947624668431880437841351583603210166158226799877881
    Line 159, in log /workspaces/repo/scratch/os_regression_2024_08_22/edn-sim-vcs/49.edn_stress_all_with_rand_reset/latest/run.log
```
  UVM_ERROR @  23996035 ps: (cip_base_vseq.sv:771) [uvm_test_top.env.virtual_sequencer.edn_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
  UVM_INFO @  23996035 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

EDN Simulation Results

Thursday August 22 2024 22:02:20 UTC

GitHub Revision: 0825c81be0

Branch: os_regression_2024_08_22

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 102736032995262985039236458937944411119924968439319752111682827040046827694889

Test Results

Testplan Progress

Coverage Results

Coverage Dashboard

Failure Buckets

Past Results

GitHub Revision: `0825c81be0`