e733a8ef8a| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | edn_smoke | 42.867s | 49 | 50 | 98.00 | |
| V1 | csr_hw_reset | edn_csr_hw_reset | 1.220s | 15.010us | 5 | 5 | 100.00 |
| V1 | csr_rw | edn_csr_rw | 1.200s | 12.264us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | edn_csr_bit_bash | 6.450s | 426.902us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | edn_csr_aliasing | 1.410s | 74.784us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | edn_csr_mem_rw_with_rand_reset | 2.310s | 36.085us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | edn_csr_rw | 1.200s | 12.264us | 20 | 20 | 100.00 |
| edn_csr_aliasing | 1.410s | 74.784us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 104 | 105 | 99.05 | |||
| V2 | firmware | edn_genbits | 1.657m | 9.114ms | 299 | 300 | 99.67 |
| V2 | csrng_commands | edn_genbits | 1.657m | 9.114ms | 299 | 300 | 99.67 |
| V2 | genbits | edn_genbits | 1.657m | 9.114ms | 299 | 300 | 99.67 |
| V2 | interrupts | edn_intr | 1.700s | 22.486us | 50 | 50 | 100.00 |
| V2 | alerts | edn_alert | 45.740s | 198 | 200 | 99.00 | |
| V2 | errs | edn_err | 1.910s | 108.256us | 100 | 100 | 100.00 |
| V2 | disable | edn_disable | 42.950s | 49 | 50 | 98.00 | |
| edn_disable_auto_req_mode | 42.917s | 49 | 50 | 98.00 | |||
| V2 | stress_all | edn_stress_all | 6.740s | 542.209us | 50 | 50 | 100.00 |
| V2 | intr_test | edn_intr_test | 1.310s | 15.326us | 50 | 50 | 100.00 |
| V2 | alert_test | edn_alert_test | 42.892s | 49 | 50 | 98.00 | |
| V2 | tl_d_oob_addr_access | edn_tl_errors | 3.580s | 103.943us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | edn_tl_errors | 3.580s | 103.943us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | edn_csr_hw_reset | 1.220s | 15.010us | 5 | 5 | 100.00 |
| edn_csr_rw | 1.200s | 12.264us | 20 | 20 | 100.00 | ||
| edn_csr_aliasing | 1.410s | 74.784us | 5 | 5 | 100.00 | ||
| edn_same_csr_outstanding | 1.730s | 42.607us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | edn_csr_hw_reset | 1.220s | 15.010us | 5 | 5 | 100.00 |
| edn_csr_rw | 1.200s | 12.264us | 20 | 20 | 100.00 | ||
| edn_csr_aliasing | 1.410s | 74.784us | 5 | 5 | 100.00 | ||
| edn_same_csr_outstanding | 1.730s | 42.607us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 934 | 940 | 99.36 | |||
| V2S | tl_intg_err | edn_sec_cm | 9.190s | 1.238ms | 5 | 5 | 100.00 |
| edn_tl_intg_err | 3.950s | 111.588us | 20 | 20 | 100.00 | ||
| V2S | sec_cm_config_regwen | edn_regwen | 1.240s | 26.459us | 10 | 10 | 100.00 |
| V2S | sec_cm_config_mubi | edn_alert | 45.740s | 198 | 200 | 99.00 | |
| V2S | sec_cm_main_sm_fsm_sparse | edn_sec_cm | 9.190s | 1.238ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ack_sm_fsm_sparse | edn_sec_cm | 9.190s | 1.238ms | 5 | 5 | 100.00 |
| V2S | sec_cm_fifo_ctr_redun | edn_sec_cm | 9.190s | 1.238ms | 5 | 5 | 100.00 |
| V2S | sec_cm_ctr_redun | edn_sec_cm | 9.190s | 1.238ms | 5 | 5 | 100.00 |
| V2S | sec_cm_main_sm_ctr_local_esc | edn_alert | 45.740s | 198 | 200 | 99.00 | |
| edn_sec_cm | 9.190s | 1.238ms | 5 | 5 | 100.00 | ||
| V2S | sec_cm_cs_rdata_bus_consistency | edn_alert | 45.740s | 198 | 200 | 99.00 | |
| V2S | sec_cm_tile_link_bus_integrity | edn_tl_intg_err | 3.950s | 111.588us | 20 | 20 | 100.00 |
| V2S | TOTAL | 35 | 35 | 100.00 | |||
| V3 | stress_all_with_rand_reset | edn_stress_all_with_rand_reset | 1.999m | 10.075ms | 29 | 50 | 58.00 |
| V3 | TOTAL | 29 | 50 | 58.00 | |||
| TOTAL | 1102 | 1130 | 97.52 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 5 | 83.33 |
| V2 | 11 | 11 | 6 | 54.55 |
| V2S | 3 | 3 | 3 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 95.90 | 98.25 | 93.91 | 97.02 | 93.02 | 96.37 | 99.77 | 92.99 |
Job timed out after * minutes has 20 failures:
1.edn_stress_all_with_rand_reset.110592617686650402192733342391777162222120149816009379936936494379501050377388
Log /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/1.edn_stress_all_with_rand_reset/latest/run.log
Job timed out after 180 minutes
4.edn_stress_all_with_rand_reset.39236351570342248073824911625931126556958787189494665897529504289388505733716
Log /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/4.edn_stress_all_with_rand_reset/latest/run.log
Job timed out after 180 minutes
... and 18 more failures.
Job returned non-zero exit code has 7 failures:
Test edn_alert has 2 failures.
17.edn_alert.58487309696184700990588334838921468037414924420814419029778567615572775327325
Log /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/17.edn_alert/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Aug 25 06:50 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
128.edn_alert.70919647849328811357385014267905967454594260427640708165137889906114408192663
Log /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/128.edn_alert/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Aug 25 06:52 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test edn_disable has 1 failures.
19.edn_disable.46902129340282476847955361061838295521327670181699801745203983505048817116795
Log /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/19.edn_disable/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Aug 25 06:50 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test edn_disable_auto_req_mode has 1 failures.
19.edn_disable_auto_req_mode.74692113236648348114906571535856015462095977802047563228969844918773218181240
Log /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/19.edn_disable_auto_req_mode/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Aug 25 06:50 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test edn_alert_test has 1 failures.
19.edn_alert_test.8314591541074588177515223784760476446282654598143096417266891361658235318525
Log /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/19.edn_alert_test/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Aug 25 06:50 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test edn_smoke has 1 failures.
20.edn_smoke.79615723221046684054455920363901029625870630288578545266676008803246140159679
Log /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/20.edn_smoke/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Aug 25 06:50 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
... and 1 more tests.
UVM_ERROR (uvm_sequencer_base.svh:757) sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'sequencer' for sequence 'm_endpoint_pull_seq[*]' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues has 1 failures:
23.edn_stress_all_with_rand_reset.58361930580809941312651016046063622430369251784496179918772391824818839663135
Line 211, in log /workspaces/repo/scratch/os_regression_2024_08_24/edn-sim-vcs/23.edn_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 878168941 ps: (uvm_sequencer_base.svh:757) uvm_test_top.env.m_endpoint_agent[0].sequencer [SEQREQZMB] The task responsible for requesting a wait_for_grant on sequencer 'uvm_test_top.env.m_endpoint_agent[0].sequencer' for sequence 'uvm_test_top.env.m_endpoint_agent[0].sequencer.m_endpoint_pull_seq[0]' has been killed, to avoid a deadlock the sequence will be removed from the arbitration queues
UVM_INFO @ 878168941 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---