EDN Simulation Results

Monday August 26 2024 23:33:20 UTC

GitHub Revision: 4674f625b3

Branch: os_regression_2024_08_26

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 27137705585251537962012108482438895412147493342955425380690984800523869492310

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.780s 34.809us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.370s 27.473us 5 5 100.00
V1 csr_rw edn_csr_rw 1.480s 16.303us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 7.070s 3.095ms 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 2.250s 70.728us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.450s 28.600us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.480s 16.303us 20 20 100.00
edn_csr_aliasing 2.250s 70.728us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 1.478m 4.577ms 300 300 100.00
V2 csrng_commands edn_genbits 1.478m 4.577ms 300 300 100.00
V2 genbits edn_genbits 1.478m 4.577ms 300 300 100.00
V2 interrupts edn_intr 1.940s 23.036us 50 50 100.00
V2 alerts edn_alert 2.070s 98.651us 200 200 100.00
V2 errs edn_err 1.980s 29.283us 100 100 100.00
V2 disable edn_disable 1.400s 12.757us 50 50 100.00
edn_disable_auto_req_mode 1.930s 111.945us 50 50 100.00
V2 stress_all edn_stress_all 8.950s 553.348us 50 50 100.00
V2 intr_test edn_intr_test 1.430s 17.744us 50 50 100.00
V2 alert_test edn_alert_test 1.600s 27.358us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 5.780s 221.833us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 5.780s 221.833us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.370s 27.473us 5 5 100.00
edn_csr_rw 1.480s 16.303us 20 20 100.00
edn_csr_aliasing 2.250s 70.728us 5 5 100.00
edn_same_csr_outstanding 2.020s 38.131us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.370s 27.473us 5 5 100.00
edn_csr_rw 1.480s 16.303us 20 20 100.00
edn_csr_aliasing 2.250s 70.728us 5 5 100.00
edn_same_csr_outstanding 2.020s 38.131us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 13.160s 1.017ms 5 5 100.00
edn_tl_intg_err 3.900s 280.567us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.630s 16.118us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 2.070s 98.651us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 13.160s 1.017ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 13.160s 1.017ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 13.160s 1.017ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 13.160s 1.017ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.070s 98.651us 200 200 100.00
edn_sec_cm 13.160s 1.017ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.070s 98.651us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 3.900s 280.567us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 3.150m 7.110ms 30 50 60.00
V3 TOTAL 30 50 60.00
TOTAL 1110 1130 98.23

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.75 98.25 93.97 97.02 91.86 96.37 99.77 92.99

Failure Buckets

Past Results