EDN Simulation Results

Wednesday August 28 2024 16:26:26 UTC

GitHub Revision: `a861deb3de`

Branch: os_regression_2024_08_28

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1071354200461384473511155521960728188378582408849032283874664554749864050652

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	edn_smoke	44.334s		49	50	98.00
V1	csr_hw_reset	edn_csr_hw_reset	1.300s	28.172us	5	5	100.00
V1	csr_rw	edn_csr_rw	1.390s	14.635us	20	20	100.00
V1	csr_bit_bash	edn_csr_bit_bash	6.560s	251.324us	5	5	100.00
V1	csr_aliasing	edn_csr_aliasing	2.220s	68.144us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	edn_csr_mem_rw_with_rand_reset	2.960s	41.638us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	edn_csr_rw	1.390s	14.635us	20	20	100.00
		edn_csr_aliasing	2.220s	68.144us	5	5	100.00
V1		TOTAL			104	105	99.05
V2	firmware	edn_genbits	4.480s	240.270us	300	300	100.00
V2	csrng_commands	edn_genbits	4.480s	240.270us	300	300	100.00
V2	genbits	edn_genbits	4.480s	240.270us	300	300	100.00
V2	interrupts	edn_intr	1.760s	23.193us	50	50	100.00
V2	alerts	edn_alert	2.210s	146.234us	200	200	100.00
V2	errs	edn_err	1.870s	24.558us	100	100	100.00
V2	disable	edn_disable	1.420s	14.019us	50	50	100.00
		edn_disable_auto_req_mode	1.810s	55.401us	50	50	100.00
V2	stress_all	edn_stress_all	44.270s		49	50	98.00
V2	intr_test	edn_intr_test	1.290s	12.575us	50	50	100.00
V2	alert_test	edn_alert_test	1.480s	17.909us	50	50	100.00
V2	tl_d_oob_addr_access	edn_tl_errors	6.020s	814.905us	20	20	100.00
V2	tl_d_illegal_access	edn_tl_errors	6.020s	814.905us	20	20	100.00
V2	tl_d_outstanding_access	edn_csr_hw_reset	1.300s	28.172us	5	5	100.00
		edn_csr_rw	1.390s	14.635us	20	20	100.00
		edn_csr_aliasing	2.220s	68.144us	5	5	100.00
		edn_same_csr_outstanding	2.050s	31.255us	20	20	100.00
V2	tl_d_partial_access	edn_csr_hw_reset	1.300s	28.172us	5	5	100.00
		edn_csr_rw	1.390s	14.635us	20	20	100.00
		edn_csr_aliasing	2.220s	68.144us	5	5	100.00
		edn_same_csr_outstanding	2.050s	31.255us	20	20	100.00
V2		TOTAL			939	940	99.89
V2S	tl_intg_err	edn_sec_cm	9.270s	622.649us	5	5	100.00
		edn_tl_intg_err	4.340s	1.129ms	20	20	100.00
V2S	sec_cm_config_regwen	edn_regwen	1.420s	52.611us	10	10	100.00
V2S	sec_cm_config_mubi	edn_alert	2.210s	146.234us	200	200	100.00
V2S	sec_cm_main_sm_fsm_sparse	edn_sec_cm	9.270s	622.649us	5	5	100.00
V2S	sec_cm_ack_sm_fsm_sparse	edn_sec_cm	9.270s	622.649us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	edn_sec_cm	9.270s	622.649us	5	5	100.00
V2S	sec_cm_ctr_redun	edn_sec_cm	9.270s	622.649us	5	5	100.00
V2S	sec_cm_main_sm_ctr_local_esc	edn_alert	2.210s	146.234us	200	200	100.00
		edn_sec_cm	9.270s	622.649us	5	5	100.00
V2S	sec_cm_cs_rdata_bus_consistency	edn_alert	2.210s	146.234us	200	200	100.00
V2S	sec_cm_tile_link_bus_integrity	edn_tl_intg_err	4.340s	1.129ms	20	20	100.00
V2S		TOTAL			35	35	100.00
V3	stress_all_with_rand_reset	edn_stress_all_with_rand_reset	1.867m	19.385ms	32	50	64.00
V3		TOTAL			32	50	64.00
		TOTAL			1110	1130	98.23

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	5	83.33
V2	11	11	10	90.91
V2S	3	3	3	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.75	98.25	93.97	97.02	91.86	96.37	99.77	92.99

Failure Buckets

Job timed out after * minutes has 18 failures:
- Test edn_stress_all_with_rand_reset has 18 failures.
  - 6.edn_stress_all_with_rand_reset.34872588531954450309105067156480955808741140819012745980060025707176971832978
    Log /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/6.edn_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 180 minutes
```
  - 8.edn_stress_all_with_rand_reset.12719633402049109067456904114423545888297281358811913586530189418547054734755
    Log /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/8.edn_stress_all_with_rand_reset/latest/run.log
```
  Job timed out after 180 minutes
```
  - ... and 16 more failures.

Job returned non-zero exit code has 2 failures:

Test edn_smoke has 1 failures.

25.edn_smoke.30517948024914698586441126312313877004362280487962711384738772610709177512687
Log /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/25.edn_smoke/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Aug 29 00:23 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255

Test edn_stress_all has 1 failures.

25.edn_stress_all.100323391074128358715181403899399936691044434418022938911083514462844487781462
Log /workspaces/repo/scratch/os_regression_2024_08_28/edn-sim-vcs/25.edn_stress_all/latest/run.log

  Chronologic VCS simulator copyright 1991-2022
  Contains Synopsys proprietary information.
  Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64;  Aug 29 00:23 2024
  Feature removed during lmreread, or wrong
  SERVER line hostid.
  Check your license file.
  
  Please contact VCS Customer Support at 1-800-VERILOG for more information.
  
  make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255