EDN Simulation Results

Sunday September 01 2024 02:56:32 UTC

GitHub Revision: ed1c41cd0f

Branch: os_regression_2024_08_31

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 79046303479535931055412478968949166876277637335647713094117953182855865639399

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.560s 18.875us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.400s 75.976us 5 5 100.00
V1 csr_rw edn_csr_rw 1.460s 17.992us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 7.460s 2.075ms 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 2.280s 71.111us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.650s 28.764us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.460s 17.992us 20 20 100.00
edn_csr_aliasing 2.280s 71.111us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 9.070s 596.717us 300 300 100.00
V2 csrng_commands edn_genbits 9.070s 596.717us 300 300 100.00
V2 genbits edn_genbits 9.070s 596.717us 300 300 100.00
V2 interrupts edn_intr 1.780s 23.324us 50 50 100.00
V2 alerts edn_alert 2.220s 254.951us 200 200 100.00
V2 errs edn_err 1.980s 30.699us 100 100 100.00
V2 disable edn_disable 1.400s 130.156us 50 50 100.00
edn_disable_auto_req_mode 2.120s 50.544us 50 50 100.00
V2 stress_all edn_stress_all 10.300s 401.877us 50 50 100.00
V2 intr_test edn_intr_test 1.330s 14.997us 50 50 100.00
V2 alert_test edn_alert_test 1.960s 52.766us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 5.160s 109.221us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 5.160s 109.221us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.400s 75.976us 5 5 100.00
edn_csr_rw 1.460s 17.992us 20 20 100.00
edn_csr_aliasing 2.280s 71.111us 5 5 100.00
edn_same_csr_outstanding 2.170s 162.740us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.400s 75.976us 5 5 100.00
edn_csr_rw 1.460s 17.992us 20 20 100.00
edn_csr_aliasing 2.280s 71.111us 5 5 100.00
edn_same_csr_outstanding 2.170s 162.740us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 11.940s 1.753ms 5 5 100.00
edn_tl_intg_err 5.150s 353.125us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.490s 18.403us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 2.220s 254.951us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 11.940s 1.753ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 11.940s 1.753ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 11.940s 1.753ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 11.940s 1.753ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.220s 254.951us 200 200 100.00
edn_sec_cm 11.940s 1.753ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.220s 254.951us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 5.150s 353.125us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 2.578m 12.308ms 32 50 64.00
V3 TOTAL 32 50 64.00
TOTAL 1112 1130 98.41

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.66 98.25 93.73 97.02 91.28 96.37 99.77 93.18

Failure Buckets

Past Results