EDN Simulation Results

Tuesday September 03 2024 20:34:49 UTC

GitHub Revision: 372a6306e0

Branch: os_regression_2024_09_03

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13282233770562214583722256565474794620746865855733889385758507057043002787586

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.610s 19.887us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.400s 20.560us 5 5 100.00
V1 csr_rw edn_csr_rw 1.390s 14.284us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 7.280s 523.129us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 2.290s 39.358us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.990s 206.212us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.390s 14.284us 20 20 100.00
edn_csr_aliasing 2.290s 39.358us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 6.450s 427.383us 300 300 100.00
V2 csrng_commands edn_genbits 6.450s 427.383us 300 300 100.00
V2 genbits edn_genbits 6.450s 427.383us 300 300 100.00
V2 interrupts edn_intr 1.890s 21.177us 50 50 100.00
V2 alerts edn_alert 2.250s 369.807us 200 200 100.00
V2 errs edn_err 2.020s 27.377us 100 100 100.00
V2 disable edn_disable 1.470s 14.732us 50 50 100.00
edn_disable_auto_req_mode 2.190s 40.980us 50 50 100.00
V2 stress_all edn_stress_all 11.270s 415.586us 50 50 100.00
V2 intr_test edn_intr_test 1.430s 17.158us 50 50 100.00
V2 alert_test edn_alert_test 2.040s 97.757us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 7.260s 1.951ms 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 7.260s 1.951ms 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.400s 20.560us 5 5 100.00
edn_csr_rw 1.390s 14.284us 20 20 100.00
edn_csr_aliasing 2.290s 39.358us 5 5 100.00
edn_same_csr_outstanding 2.480s 177.839us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.400s 20.560us 5 5 100.00
edn_csr_rw 1.390s 14.284us 20 20 100.00
edn_csr_aliasing 2.290s 39.358us 5 5 100.00
edn_same_csr_outstanding 2.480s 177.839us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 12.850s 1.090ms 5 5 100.00
edn_tl_intg_err 4.640s 173.401us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.570s 19.654us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 2.250s 369.807us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 12.850s 1.090ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 12.850s 1.090ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 12.850s 1.090ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 12.850s 1.090ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.250s 369.807us 200 200 100.00
edn_sec_cm 12.850s 1.090ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.250s 369.807us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 4.640s 173.401us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 2.509m 19.194ms 28 50 56.00
V3 TOTAL 28 50 56.00
TOTAL 1108 1130 98.05

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.80 98.25 93.97 97.02 91.86 96.37 99.77 93.37

Failure Buckets

Past Results