EDN Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: af2d1709f9

Branch: os_regression_2024_09_08

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.520s 18.908us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.350s 70.619us 5 5 100.00
V1 csr_rw edn_csr_rw 1.350s 24.391us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 4.080s 238.751us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.890s 157.391us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.180s 54.573us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.350s 24.391us 20 20 100.00
edn_csr_aliasing 1.890s 157.391us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 7.630s 1.161ms 300 300 100.00
V2 csrng_commands edn_genbits 7.630s 1.161ms 300 300 100.00
V2 genbits edn_genbits 7.630s 1.161ms 300 300 100.00
V2 interrupts edn_intr 1.780s 21.284us 50 50 100.00
V2 alerts edn_alert 2.030s 31.656us 200 200 100.00
V2 errs edn_err 2.040s 59.574us 100 100 100.00
V2 disable edn_disable 1.430s 14.160us 50 50 100.00
edn_disable_auto_req_mode 2.050s 45.396us 50 50 100.00
V2 stress_all edn_stress_all 7.570s 1.009ms 50 50 100.00
V2 intr_test edn_intr_test 1.470s 15.622us 50 50 100.00
V2 alert_test edn_alert_test 1.510s 24.510us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.420s 979.385us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.420s 979.385us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.350s 70.619us 5 5 100.00
edn_csr_rw 1.350s 24.391us 20 20 100.00
edn_csr_aliasing 1.890s 157.391us 5 5 100.00
edn_same_csr_outstanding 1.820s 34.052us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.350s 70.619us 5 5 100.00
edn_csr_rw 1.350s 24.391us 20 20 100.00
edn_csr_aliasing 1.890s 157.391us 5 5 100.00
edn_same_csr_outstanding 1.820s 34.052us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 13.650s 1.315ms 5 5 100.00
edn_tl_intg_err 4.200s 194.186us 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.570s 20.133us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 2.030s 31.656us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 13.650s 1.315ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 13.650s 1.315ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 13.650s 1.315ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 13.650s 1.315ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.030s 31.656us 200 200 100.00
edn_sec_cm 13.650s 1.315ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.030s 31.656us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 4.200s 194.186us 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 2.410m 20.033ms 33 50 66.00
V3 TOTAL 33 50 66.00
TOTAL 1113 1130 98.50

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.83 98.25 93.79 97.02 92.44 96.37 99.77 93.18

Failure Buckets

Past Results