EDN Simulation Results

Tuesday September 10 2024 22:04:06 UTC

GitHub Revision: 25b1acbf68

Branch: os_regression_2024_09_10

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115096073277204595231937901342804627564470767004707790242822318429579153097636

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke edn_smoke 1.550s 19.409us 50 50 100.00
V1 csr_hw_reset edn_csr_hw_reset 1.410s 28.274us 5 5 100.00
V1 csr_rw edn_csr_rw 1.300s 50.968us 20 20 100.00
V1 csr_bit_bash edn_csr_bit_bash 7.820s 523.893us 5 5 100.00
V1 csr_aliasing edn_csr_aliasing 1.730s 21.914us 5 5 100.00
V1 csr_mem_rw_with_rand_reset edn_csr_mem_rw_with_rand_reset 2.280s 103.785us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr edn_csr_rw 1.300s 50.968us 20 20 100.00
edn_csr_aliasing 1.730s 21.914us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware edn_genbits 2.237m 16.940ms 300 300 100.00
V2 csrng_commands edn_genbits 2.237m 16.940ms 300 300 100.00
V2 genbits edn_genbits 2.237m 16.940ms 300 300 100.00
V2 interrupts edn_intr 1.850s 25.278us 50 50 100.00
V2 alerts edn_alert 2.200s 253.126us 200 200 100.00
V2 errs edn_err 1.980s 35.689us 100 100 100.00
V2 disable edn_disable 1.430s 13.629us 50 50 100.00
edn_disable_auto_req_mode 2.230s 45.594us 50 50 100.00
V2 stress_all edn_stress_all 9.730s 423.254us 50 50 100.00
V2 intr_test edn_intr_test 1.300s 12.640us 50 50 100.00
V2 alert_test edn_alert_test 1.530s 19.788us 50 50 100.00
V2 tl_d_oob_addr_access edn_tl_errors 4.690s 251.736us 20 20 100.00
V2 tl_d_illegal_access edn_tl_errors 4.690s 251.736us 20 20 100.00
V2 tl_d_outstanding_access edn_csr_hw_reset 1.410s 28.274us 5 5 100.00
edn_csr_rw 1.300s 50.968us 20 20 100.00
edn_csr_aliasing 1.730s 21.914us 5 5 100.00
edn_same_csr_outstanding 1.980s 65.292us 20 20 100.00
V2 tl_d_partial_access edn_csr_hw_reset 1.410s 28.274us 5 5 100.00
edn_csr_rw 1.300s 50.968us 20 20 100.00
edn_csr_aliasing 1.730s 21.914us 5 5 100.00
edn_same_csr_outstanding 1.980s 65.292us 20 20 100.00
V2 TOTAL 940 940 100.00
V2S tl_intg_err edn_sec_cm 14.140s 1.049ms 5 5 100.00
edn_tl_intg_err 14.470s 1.245ms 20 20 100.00
V2S sec_cm_config_regwen edn_regwen 1.570s 16.697us 10 10 100.00
V2S sec_cm_config_mubi edn_alert 2.200s 253.126us 200 200 100.00
V2S sec_cm_main_sm_fsm_sparse edn_sec_cm 14.140s 1.049ms 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse edn_sec_cm 14.140s 1.049ms 5 5 100.00
V2S sec_cm_fifo_ctr_redun edn_sec_cm 14.140s 1.049ms 5 5 100.00
V2S sec_cm_ctr_redun edn_sec_cm 14.140s 1.049ms 5 5 100.00
V2S sec_cm_main_sm_ctr_local_esc edn_alert 2.200s 253.126us 200 200 100.00
edn_sec_cm 14.140s 1.049ms 5 5 100.00
V2S sec_cm_cs_rdata_bus_consistency edn_alert 2.200s 253.126us 200 200 100.00
V2S sec_cm_tile_link_bus_integrity edn_tl_intg_err 14.470s 1.245ms 20 20 100.00
V2S TOTAL 35 35 100.00
V3 stress_all_with_rand_reset edn_stress_all_with_rand_reset 2.863h 10.000s 25 50 50.00
V3 TOTAL 25 50 50.00
TOTAL 1105 1130 97.79

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 11 11 11 100.00
V2S 3 3 3 100.00
V3 1 1 0 0.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.78 98.25 93.97 97.07 91.86 96.37 99.77 93.18

Failure Buckets

Past Results