ENTROPY_SRC Simulation Results

Tuesday July 09 2024 23:02:48 UTC

GitHub Revision: 6a84251492

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 61727890964832844865465694323650730626175387240181955975848876152363892893427

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 8.000s 78.547us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 4.000s 24.955us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 12.000s 27.372us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 14.000s 797.145us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 7.000s 81.625us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 9.000s 108.688us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 12.000s 27.372us 20 20 100.00
entropy_src_csr_aliasing 7.000s 81.625us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 8.000s 78.547us 50 50 100.00
entropy_src_rng 4.850m 10.058ms 300 300 100.00
entropy_src_fw_ov 2.417m 5.071ms 281 300 93.67
V2 firmware_mode entropy_src_fw_ov 2.417m 5.071ms 281 300 93.67
V2 rng_mode entropy_src_rng 4.850m 10.058ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 9.300m 10.096ms 396 400 99.00
V2 health_checks entropy_src_rng 4.850m 10.058ms 300 300 100.00
V2 conditioning entropy_src_rng 4.850m 10.058ms 300 300 100.00
V2 interrupts entropy_src_rng 4.850m 10.058ms 300 300 100.00
entropy_src_intr 30.000s 1.940ms 50 50 100.00
V2 alerts entropy_src_rng 4.850m 10.058ms 300 300 100.00
entropy_src_functional_alerts 9.000s 120.145us 50 50 100.00
V2 stress_all entropy_src_stress_all 14.000s 361.870us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.967m 10.012ms 979 1000 97.90
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 23.000s 696.017us 50 50 100.00
V2 intr_test entropy_src_intr_test 7.000s 18.743us 50 50 100.00
V2 alert_test entropy_src_alert_test 8.000s 25.989us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 12.000s 242.741us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 12.000s 242.741us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 4.000s 24.955us 5 5 100.00
entropy_src_csr_rw 12.000s 27.372us 20 20 100.00
entropy_src_csr_aliasing 7.000s 81.625us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 1.008ms 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 4.000s 24.955us 5 5 100.00
entropy_src_csr_rw 12.000s 27.372us 20 20 100.00
entropy_src_csr_aliasing 7.000s 81.625us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 1.008ms 20 20 100.00
V2 TOTAL 2296 2340 98.12
V2S tl_intg_err entropy_src_sec_cm 8.000s 87.531us 5 5 100.00
entropy_src_tl_intg_err 8.000s 118.520us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.850m 10.058ms 300 300 100.00
entropy_src_cfg_regwen 13.000s 214.832us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.850m 10.058ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 4.850m 10.058ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 4.850m 10.058ms 300 300 100.00
entropy_src_fw_ov 2.417m 5.071ms 281 300 93.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.967m 10.012ms 979 1000 97.90
entropy_src_sec_cm 8.000s 87.531us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.967m 10.012ms 979 1000 97.90
entropy_src_sec_cm 8.000s 87.531us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.850m 10.058ms 300 300 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.967m 10.012ms 979 1000 97.90
entropy_src_sec_cm 8.000s 87.531us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.967m 10.012ms 979 1000 97.90
entropy_src_sec_cm 8.000s 87.531us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.967m 10.012ms 979 1000 97.90
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 9.000s 120.145us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 8.000s 118.520us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.583m 10.032ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
TOTAL 2526 2570 98.29

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 9 75.00
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.10 98.15 95.32 98.33 95.79 96.62 96.88 90.48 95.70

Failure Buckets

Past Results