ENTROPY_SRC Simulation Results

Wednesday July 10 2024 23:02:26 UTC

GitHub Revision: 39211701b5

Branch: os_regression

Testplan

Simulator: XCELIUM

Build randomization enabled with --build-seed 52262812535389540465251148247405743574935129745685597413714598750252192397067

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke entropy_src_smoke 11.000s 55.491us 50 50 100.00
V1 csr_hw_reset entropy_src_csr_hw_reset 8.000s 161.452us 5 5 100.00
V1 csr_rw entropy_src_csr_rw 8.000s 62.076us 20 20 100.00
V1 csr_bit_bash entropy_src_csr_bit_bash 13.000s 540.311us 5 5 100.00
V1 csr_aliasing entropy_src_csr_aliasing 8.000s 732.350us 5 5 100.00
V1 csr_mem_rw_with_rand_reset entropy_src_csr_mem_rw_with_rand_reset 8.000s 83.544us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr entropy_src_csr_rw 8.000s 62.076us 20 20 100.00
entropy_src_csr_aliasing 8.000s 732.350us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 firmware entropy_src_smoke 11.000s 55.491us 50 50 100.00
entropy_src_rng 4.717m 10.075ms 300 300 100.00
entropy_src_fw_ov 2.450m 5.017ms 287 300 95.67
V2 firmware_mode entropy_src_fw_ov 2.450m 5.017ms 287 300 95.67
V2 rng_mode entropy_src_rng 4.717m 10.075ms 300 300 100.00
V2 rng_max_rate entropy_src_rng_max_rate 8.633m 10.065ms 398 400 99.50
V2 health_checks entropy_src_rng 4.717m 10.075ms 300 300 100.00
V2 conditioning entropy_src_rng 4.717m 10.075ms 300 300 100.00
V2 interrupts entropy_src_rng 4.717m 10.075ms 300 300 100.00
entropy_src_intr 19.000s 2.274ms 50 50 100.00
V2 alerts entropy_src_rng 4.717m 10.075ms 300 300 100.00
entropy_src_functional_alerts 13.000s 53.785us 50 50 100.00
V2 stress_all entropy_src_stress_all 14.000s 335.044us 50 50 100.00
V2 functional_errors entropy_src_functional_errors 9.917m 10.013ms 961 1000 96.10
V2 firmware_ov_read_contiguous_data entropy_src_fw_ov_contiguous 29.000s 1.350ms 49 50 98.00
V2 intr_test entropy_src_intr_test 8.000s 22.688us 50 50 100.00
V2 alert_test entropy_src_alert_test 18.000s 15.483us 50 50 100.00
V2 tl_d_oob_addr_access entropy_src_tl_errors 8.000s 637.249us 20 20 100.00
V2 tl_d_illegal_access entropy_src_tl_errors 8.000s 637.249us 20 20 100.00
V2 tl_d_outstanding_access entropy_src_csr_hw_reset 8.000s 161.452us 5 5 100.00
entropy_src_csr_rw 8.000s 62.076us 20 20 100.00
entropy_src_csr_aliasing 8.000s 732.350us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 97.279us 20 20 100.00
V2 tl_d_partial_access entropy_src_csr_hw_reset 8.000s 161.452us 5 5 100.00
entropy_src_csr_rw 8.000s 62.076us 20 20 100.00
entropy_src_csr_aliasing 8.000s 732.350us 5 5 100.00
entropy_src_same_csr_outstanding 5.000s 97.279us 20 20 100.00
V2 TOTAL 2285 2340 97.65
V2S tl_intg_err entropy_src_sec_cm 8.000s 56.883us 5 5 100.00
entropy_src_tl_intg_err 10.000s 107.183us 20 20 100.00
V2S sec_cm_config_regwen entropy_src_rng 4.717m 10.075ms 300 300 100.00
entropy_src_cfg_regwen 13.000s 30.513us 50 50 100.00
V2S sec_cm_config_mubi entropy_src_rng 4.717m 10.075ms 300 300 100.00
V2S sec_cm_config_redun entropy_src_rng 4.717m 10.075ms 300 300 100.00
V2S sec_cm_intersig_mubi entropy_src_rng 4.717m 10.075ms 300 300 100.00
entropy_src_fw_ov 2.450m 5.017ms 287 300 95.67
V2S sec_cm_main_sm_fsm_sparse entropy_src_functional_errors 9.917m 10.013ms 961 1000 96.10
entropy_src_sec_cm 8.000s 56.883us 5 5 100.00
V2S sec_cm_ack_sm_fsm_sparse entropy_src_functional_errors 9.917m 10.013ms 961 1000 96.10
entropy_src_sec_cm 8.000s 56.883us 5 5 100.00
V2S sec_cm_rng_bkgn_chk entropy_src_rng 4.717m 10.075ms 300 300 100.00
V2S sec_cm_fifo_ctr_redun entropy_src_functional_errors 9.917m 10.013ms 961 1000 96.10
entropy_src_sec_cm 8.000s 56.883us 5 5 100.00
V2S sec_cm_ctr_redun entropy_src_functional_errors 9.917m 10.013ms 961 1000 96.10
entropy_src_sec_cm 8.000s 56.883us 5 5 100.00
V2S sec_cm_ctr_local_esc entropy_src_functional_errors 9.917m 10.013ms 961 1000 96.10
V2S sec_cm_esfinal_rdata_bus_consistency entropy_src_functional_alerts 13.000s 53.785us 50 50 100.00
V2S sec_cm_tile_link_bus_integrity entropy_src_tl_intg_err 10.000s 107.183us 20 20 100.00
V2S TOTAL 75 75 100.00
V3 external_health_tests entropy_src_rng_with_xht_rsps 4.500m 10.040ms 50 50 100.00
V3 stress_all_with_rand_reset entropy_src_stress_all_with_rand_reset 0 0 --
V3 TOTAL 50 50 100.00
TOTAL 2515 2570 97.86

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 8 66.67
V2S 3 3 3 100.00
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

Score Block Branch Statement Expression Toggle Fsm Assertion CoverGroup
97.10 98.15 95.32 98.33 95.79 96.62 96.88 90.48 95.70

Failure Buckets

Past Results