FLASH_CTRL Simulation Results

Monday May 22 2023 07:05:49 UTC

GitHub Revision: `e3fb01b5e`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 3641199223

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.630m	43.955us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.040s	166.682us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.380s	96.701us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.570s	129.051us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.110m	4.795ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.069m	1.363ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	18.970s	36.214us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.570s	129.051us	20	20	100.00
		flash_ctrl_csr_aliasing	1.069m	1.363ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.480s	34.754us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.300s	16.516us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.650s	92.791us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.908m	245.641us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	28.126m	1.143s	3	3	100.00
		flash_ctrl_hw_rma_reset	13.969m	760.531ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.220s	25.625us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	39.712m	240.527ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.474m	6.709ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	26.720s	730.762us	29	30	96.67
V2	full_memory_access	flash_ctrl_full_mem_access	59.097m	1.149s	3	5	60.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.125m	1.833ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	38.020s	111.864us	40	40	100.00
		flash_ctrl_rw_evict_all_en	36.520s	115.249us	37	40	92.50
		flash_ctrl_re_evict	39.820s	136.740us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.538m	4.166ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.538m	4.166ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	18.205m	55.541ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	29.680s	1.573ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	23.406m	2.113ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	43.046m	7.579ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	15.888m	2.896ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	45.829m	3.361ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.810s	25.712us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	6.813m	2.524ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.060s	131.120us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.270s	100.163us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	31.935m	450.281us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.415m	12.636ms	50	50	100.00
		flash_ctrl_otp_reset	2.276m	80.830us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	28.126m	1.143s	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	7.677m	5.397ms	40	40	100.00
		flash_ctrl_intr_wr	2.386m	47.197ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	10.656m	72.451ms	39	40	97.50
		flash_ctrl_intr_wr_slow_flash	10.138m	104.436ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.687m	4.752ms	15	20	75.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	31.560s	4.397ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.110s	21.348us	5	5	100.00
		flash_ctrl_ro_derr	6.317m	3.546ms	10	10	100.00
		flash_ctrl_rw_derr	29.181m	6.150ms	10	10	100.00
		flash_ctrl_derr_detect	1.815m	387.982us	5	5	100.00
		flash_ctrl_integrity	29.378m	6.080ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.470s	24.850us	5	5	100.00
		flash_ctrl_ro_serr	6.308m	1.754ms	10	10	100.00
		flash_ctrl_rw_serr	28.488m	27.238ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.479m	835.283us	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.668m	995.569us	5	5	100.00
V2	scramble	flash_ctrl_wo	3.505m	9.559ms	20	20	100.00
		flash_ctrl_write_word_sweep	16.810s	62.304us	1	1	100.00
		flash_ctrl_read_word_sweep	14.350s	82.588us	1	1	100.00
		flash_ctrl_ro	5.128m	2.445ms	20	20	100.00
		flash_ctrl_rw	27.158m	60.908ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	37.080s	2.092ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	14.377m	49.719ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	4.627m	10.005ms	17	20	85.00
V2	alert_test	flash_ctrl_alert_test	14.340s	171.308us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.840s	15.440us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.650s	304.178us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.650s	304.178us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.380s	96.701us	5	5	100.00
		flash_ctrl_csr_rw	17.570s	129.051us	20	20	100.00
		flash_ctrl_csr_aliasing	1.069m	1.363ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.930s	325.003us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.380s	96.701us	5	5	100.00
		flash_ctrl_csr_rw	17.570s	129.051us	20	20	100.00
		flash_ctrl_csr_aliasing	1.069m	1.363ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.930s	325.003us	20	20	100.00
V2		TOTAL			998	1013	98.52
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	2.254m	272.949us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	2.254m	272.949us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	2.254m	272.949us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	2.254m	272.949us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	2.029m	145.901us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.374h	1.260ms	4	5	80.00
		flash_ctrl_tl_intg_err	15.014m	1.327ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.014m	1.327ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.014m	1.327ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	33.090s	325.262us	3	3	100.00
		flash_ctrl_wr_intg	15.250s	187.951us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.630m	43.955us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.276m	80.830us	80	80	100.00
		flash_ctrl_disable	23.060s	131.120us	50	50	100.00
		flash_ctrl_sec_info_access	1.407m	16.400ms	50	50	100.00
		flash_ctrl_connect	16.270s	100.163us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.270s	21.284us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.570s	129.051us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	2.254m	272.949us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.570s	129.051us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	2.254m	272.949us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.570s	129.051us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	2.254m	272.949us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.060s	131.120us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	33.090s	325.262us	3	3	100.00
		flash_ctrl_access_after_disable	13.700s	14.228us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.060s	131.120us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	29.680s	1.573ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	27.158m	60.908ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	28.488m	27.238ms	10	10	100.00
		flash_ctrl_rw_derr	29.181m	6.150ms	10	10	100.00
		flash_ctrl_integrity	29.378m	6.080ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	28.126m	1.143s	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.374h	1.260ms	4	5	80.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.374h	1.260ms	4	5	80.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.374h	1.260ms	4	5	80.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.374h	1.260ms	4	5	80.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	14.610s	63.905us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	13.970s	10.856us	3	5	60.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.850s	25.594us	3	5	60.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.374h	1.260ms	4	5	80.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.374h	1.260ms	4	5	80.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.374h	1.260ms	4	5	80.00
V2S		TOTAL			139	144	96.53
V3	asymmetric_read_path	flash_ctrl_rd_ooo	44.670s	196.993us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1258	1278	98.44

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	49	89.09
V2S	12	12	9	75.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.45	95.50	94.48	98.95	91.84	97.36	98.30	98.75

Failure Buckets

UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 3 failures:

Test flash_ctrl_invalid_op has 3 failures.

3.flash_ctrl_invalid_op.1596759010
Line 5229, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 9182611.0 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 9182611.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

15.flash_ctrl_invalid_op.1338314343
Line 2658, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 806313.2 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 806313.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:479) [lm_wdata_comp_bank1] Check failed rcv.mem_addr == exp.req.addr (* [*] vs * [*]) has 3 failures:
- Test flash_ctrl_hw_prog_rma_wipe_err has 3 failures.
  - 5.flash_ctrl_hw_prog_rma_wipe_err.2061672764
    Line 269, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_hw_prog_rma_wipe_err/latest/run.log
```
  UVM_ERROR @ 10005562.3 ns: (flash_ctrl_otf_scoreboard.sv:479) [lm_wdata_comp_bank1] Check failed rcv.mem_addr == exp.req.addr (0 [0x0] vs 28883 [0x70d3])
  UVM_INFO @ 10005562.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 12.flash_ctrl_hw_prog_rma_wipe_err.664261755
    Line 269, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_hw_prog_rma_wipe_err/latest/run.log
```
  UVM_ERROR @ 10004722.3 ns: (flash_ctrl_otf_scoreboard.sv:479) [lm_wdata_comp_bank1] Check failed rcv.mem_addr == exp.req.addr (0 [0x0] vs 28822 [0x7096])
  UVM_INFO @ 10004722.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 2 failures:
- Test flash_ctrl_full_mem_access has 2 failures.
  - 0.flash_ctrl_full_mem_access.2534874863
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:05d00314-eff6-496a-ab31-b8875cca657a
```
  - 4.flash_ctrl_full_mem_access.1386790522
    Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_full_mem_access/latest/run.log
```
  Job ID: smart:2b902324-9651-4a41-981a-a6f386c65b5b
```

Offending '(!$isunknown(mem_tl_o.d_valid))' has 2 failures:

Test flash_ctrl_phy_host_grant_err has 2 failures.

2.flash_ctrl_phy_host_grant_err.2282345085
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_phy_host_grant_err/latest/run.log

      Offending '(!$isunknown(mem_tl_o.d_valid))'
  UVM_ERROR @ 10855.6 ns: (flash_ctrl.sv:1397) [ASSERT FAILED] MemTlDValidKnownO_A
  UVM_INFO @ 10855.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_phy_host_grant_err.1856491982
Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_phy_host_grant_err/latest/run.log

      Offending '(!$isunknown(mem_tl_o.d_valid))'
  UVM_ERROR @ 57889.5 ns: (flash_ctrl.sv:1397) [ASSERT FAILED] MemTlDValidKnownO_A
  UVM_INFO @ 57889.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 2 failures:

Test flash_ctrl_rw_evict_all_en has 2 failures.

3.flash_ctrl_rw_evict_all_en.50070136
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 87880.0 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 87880.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

30.flash_ctrl_rw_evict_all_en.2961415938
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 147949.6 ns: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 147949.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:221) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert recov_err triggered unexpectedly has 2 failures:

Test flash_ctrl_invalid_op has 2 failures.

4.flash_ctrl_invalid_op.1519282561
Line 829, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 692762.4 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 692762.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.flash_ctrl_invalid_op.1964473334
Line 421, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_invalid_op/latest/run.log

  UVM_ERROR @ 152308.9 ns: (cip_base_scoreboard.sv:221) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert recov_err triggered unexpectedly
  UVM_INFO @ 152308.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_scoreboard.sv:431) [mon_tb_mem0] Check failed cfg.flash_ctrl_mem_vif[bank].info0_mem_req == * (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_prog_reset has 1 failures.
  - 1.flash_ctrl_prog_reset.2233931640
    Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_prog_reset/latest/run.log
```
  UVM_ERROR @ 38661.0 ns: (flash_ctrl_otf_scoreboard.sv:431) [mon_tb_mem0] Check failed cfg.flash_ctrl_mem_vif[bank].info0_mem_req == 1 (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 38661.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Offending '(!$isunknown(rdata_o))' has 1 failures:

Test flash_ctrl_sec_cm has 1 failures.

1.flash_ctrl_sec_cm.1198329862
Line 7285, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_sec_cm/latest/run.log

      Offending '(!$isunknown(rdata_o))'
  UVM_ERROR @ 1095976.0 ns: (prim_fifo_sync.sv:193) [ASSERT FAILED] DataKnown_A
  UVM_INFO @ 1095976.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:281) scoreboard [scoreboard] alert fatal_err did not trigger max_delay:* has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 2.flash_ctrl_phy_ack_consistency.657962283
    Line 262, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 25594.2 ns: (cip_base_scoreboard.sv:281) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_err did not trigger max_delay:2000
  UVM_INFO @ 25594.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '$past(clr_i)' has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 4.flash_ctrl_phy_ack_consistency.2211781707
    Line 263, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_phy_ack_consistency/latest/run.log
```
      Offending '$past(clr_i)'
  UVM_ERROR @ 10147.2 ns: (prim_count.sv:167) [ASSERT FAILED] ClrBkwd_A
  UVM_INFO @ 10147.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_phy_prim_monitor.sv:44) [monitor] timeout waiting for mon_start has 1 failures:
- Test flash_ctrl_intr_rd_slow_flash has 1 failures.
  - 38.flash_ctrl_intr_rd_slow_flash.792972527
    Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd_slow_flash/latest/run.log
```
  UVM_FATAL @ 200000.0 ns: (flash_phy_prim_monitor.sv:44) [uvm_test_top.env.m_fpp_agent.monitor] timeout waiting for mon_start
  UVM_INFO @ 200000.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (flash_ctrl_scoreboard.sv:819) [scoreboard] Check failed item.d_error == * (* [*] vs * [*]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@157317) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_source_is_overridden: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test flash_ctrl_rw_evict_all_en has 1 failures.

38.flash_ctrl_rw_evict_all_en.1288612231
Line 261, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 23424.7 ns: (flash_ctrl_scoreboard.sv:819) [uvm_test_top.env.scoreboard] Check failed item.d_error == 1 (0 [0x0] vs 1 [0x1]) On interface flash_ctrl_eflash_reg_block, TL item: req: (cip_tl_seq_item@157317) { a_addr: 'h61350  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h8b  a_opcode: 'h4  a_user: 'h275aa  d_param: 'h0  d_source: 'h8b  d_data: 'h3ca6c9c2  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd0f  a_source_is_overridden: 'h0  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , ecc_err:1 in_err:0
  UVM_INFO @ 23424.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---