FLASH_CTRL Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: c30684b3ca

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.658m	64.790us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.360s	63.013us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	47.100s	29.145us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.160s	160.597us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.540m	10.217ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.087m	6.572ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	21.730s	47.083us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.160s	160.597us	20	20	100.00
		flash_ctrl_csr_aliasing	1.087m	6.572ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	14.120s	16.194us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.650s	106.566us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.680s	54.713us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.698m	58.529us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	31.226m	271.931ms	3	3	100.00
		flash_ctrl_hw_rma_reset	15.226m	160.187ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.960s	26.476us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	45.542m	301.476ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.270m	13.399ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	1.044m	3.060ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	41.098m	86.431ms	1	5	20.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.156m	1.726ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	36.280s	185.634us	40	40	100.00
		flash_ctrl_rw_evict_all_en	36.720s	101.355us	40	40	100.00
		flash_ctrl_re_evict	41.090s	507.151us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.408m	2.121ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.408m	2.121ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	19.746m	27.834ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	27.090s	475.841us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	21.548m	1.631ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	38.749m	6.161ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.826m	3.010ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	39.852m	923.052us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.970s	48.526us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.037m	6.059ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.650s	21.996us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.750s	25.413us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	22.706m	1.957ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.544m	18.862ms	50	50	100.00
		flash_ctrl_otp_reset	2.306m	47.466us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	31.226m	271.931ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.683m	3.643ms	40	40	100.00
		flash_ctrl_intr_wr	1.748m	9.139ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	5.240m	118.905ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	8.661m	231.992ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.812m	19.266ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.232m	1.839ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.150s	33.901us	5	5	100.00
		flash_ctrl_ro_derr	2.554m	2.603ms	10	10	100.00
		flash_ctrl_rw_derr	11.883m	19.222ms	9	10	90.00
		flash_ctrl_derr_detect	1.771m	147.908us	5	5	100.00
		flash_ctrl_integrity	11.217m	5.726ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.140s	40.954us	5	5	100.00
		flash_ctrl_ro_serr	2.499m	741.670us	10	10	100.00
		flash_ctrl_rw_serr	10.812m	7.753ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.743m	6.386ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.317m	3.306ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.755m	21.989ms	20	20	100.00
		flash_ctrl_write_word_sweep	16.250s	246.497us	1	1	100.00
		flash_ctrl_read_word_sweep	14.370s	26.100us	1	1	100.00
		flash_ctrl_ro	2.022m	370.927us	20	20	100.00
		flash_ctrl_rw	11.427m	33.661ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	37.710s	902.497us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	21.046m	95.293ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	4.891m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.470s	46.920us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.960s	14.319us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	18.660s	135.050us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	18.660s	135.050us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	47.100s	29.145us	5	5	100.00
		flash_ctrl_csr_rw	18.160s	160.597us	20	20	100.00
		flash_ctrl_csr_aliasing	1.087m	6.572ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	38.690s	2.495ms	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	47.100s	29.145us	5	5	100.00
		flash_ctrl_csr_rw	18.160s	160.597us	20	20	100.00
		flash_ctrl_csr_aliasing	1.087m	6.572ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	38.690s	2.495ms	20	20	100.00
V2		TOTAL			1008	1013	99.51
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.120s	20.619us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.120s	20.619us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.120s	20.619us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.120s	20.619us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.020s	45.112us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.335h	1.291ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.154m	6.461ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.154m	6.461ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.154m	6.461ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.330s	209.433us	3	3	100.00
		flash_ctrl_wr_intg	14.940s	85.465us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.658m	64.790us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.306m	47.466us	80	80	100.00
		flash_ctrl_disable	22.650s	21.996us	50	50	100.00
		flash_ctrl_sec_info_access	1.491m	22.995ms	50	50	100.00
		flash_ctrl_connect	16.750s	25.413us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.930s	69.793us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.160s	160.597us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.120s	20.619us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.160s	160.597us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.120s	20.619us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.160s	160.597us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.120s	20.619us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.650s	21.996us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.330s	209.433us	3	3	100.00
		flash_ctrl_access_after_disable	14.080s	13.795us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.650s	21.996us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	27.090s	475.841us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.427m	33.661ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	10.812m	7.753ms	10	10	100.00
		flash_ctrl_rw_derr	11.883m	19.222ms	9	10	90.00
		flash_ctrl_integrity	11.217m	5.726ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	31.226m	271.931ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.335h	1.291ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.335h	1.291ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.335h	1.291ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.335h	1.291ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	55.780s	699.558us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	13.900s	56.807us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.420s	68.141us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.335h	1.291ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.335h	1.291ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.335h	1.291ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	42.900s	38.514us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1273	1278	99.61

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	53	96.36
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.61	95.77	94.28	98.95	92.52	98.24	98.30	98.21

Failure Buckets

• Job flash_ctrl-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 4 failures:
  • Test flash_ctrl_full_mem_access has 4 failures.

    • 0.flash_ctrl_full_mem_access.54168264254709309986730534351296569698204894168296023487015695011260716539758
      Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_full_mem_access/latest/run.log

        Job ID: smart:e222111f-1bf0-412e-93c0-b9aeea502f8d
      

    • 1.flash_ctrl_full_mem_access.25201022992740053752631145663118844035230225708978852064729609829051484042168
      Log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_full_mem_access/latest/run.log

        Job ID: smart:3f3f3d2f-0cbd-4f73-83dd-fa318b434ca8
      

    • ... and 2 more failures.

• UVM_ERROR (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (* [*] vs * [*]) has 1 failures:
  • Test flash_ctrl_rw_derr has 1 failures.

    • 4.flash_ctrl_rw_derr.54460241884370162741886376797536882183458650321025227584139819335871345478301
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest/run.log

        UVM_ERROR @ 3152151.0 ns: (flash_ctrl_otf_scoreboard.sv:547) [lm_wdata_comp_bank0] Check failed rcv.mem_wdata == exp.req.prog_full_data (148726962107038571162 [0x81000500c11041a9a] vs 148726962106770135706 [0x81000500c01041a9a])
        UVM_INFO @ 3152151.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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