FLASH_CTRL Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: 36c168c253

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.307m	1.413ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	27.250s	33.922us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.410s	177.280us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.300s	797.349us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.337m	9.252ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.050m	2.536ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.800s	109.758us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.300s	797.349us	20	20	100.00
		flash_ctrl_csr_aliasing	1.050m	2.536ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	14.210s	101.141us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.600s	19.877us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.650s	37.222us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.100m	67.477us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	33.324m	125.677ms	3	3	100.00
		flash_ctrl_hw_rma_reset	15.833m	260.211ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.990s	48.715us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	42.678m	265.687ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	7.233m	8.514ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	46.810s	2.124ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.311h	187.826ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.324m	1.404ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	36.840s	175.206us	40	40	100.00
		flash_ctrl_rw_evict_all_en	40.350s	246.802us	40	40	100.00
		flash_ctrl_re_evict	40.800s	486.780us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.825m	1.397ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.825m	1.397ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	21.956m	189.235ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	29.810s	415.959us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	20.746m	8.205ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	43.835m	41.777ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.398m	4.269ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	40.067m	1.779ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.240s	44.748us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.456m	5.942ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.710s	12.955us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.370s	30.393us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	20.455m	284.159us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.532m	12.222ms	50	50	100.00
		flash_ctrl_otp_reset	2.298m	38.646us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	33.324m	125.677ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.687m	14.509ms	40	40	100.00
		flash_ctrl_intr_wr	2.130m	44.311ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	5.057m	8.389ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	6.730m	423.335ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.627m	1.161ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.257m	993.261us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.400s	17.835us	5	5	100.00
		flash_ctrl_ro_derr	2.938m	636.888us	10	10	100.00
		flash_ctrl_rw_derr	10.711m	13.489ms	10	10	100.00
		flash_ctrl_derr_detect	1.794m	544.622us	5	5	100.00
		flash_ctrl_integrity	13.617m	91.020ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.940s	96.856us	5	5	100.00
		flash_ctrl_ro_serr	2.708m	1.933ms	10	10	100.00
		flash_ctrl_rw_serr	11.670m	22.509ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.397m	9.375ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.380m	1.408ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.852m	50.667ms	20	20	100.00
		flash_ctrl_write_word_sweep	17.540s	67.155us	1	1	100.00
		flash_ctrl_read_word_sweep	13.700s	15.344us	1	1	100.00
		flash_ctrl_ro	2.176m	2.195ms	20	20	100.00
		flash_ctrl_rw	10.212m	3.629ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	40.520s	1.297ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	15.348m	157.535ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.362m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.440s	47.278us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.870s	183.060us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.300s	804.031us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.300s	804.031us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.410s	177.280us	5	5	100.00
		flash_ctrl_csr_rw	18.300s	797.349us	20	20	100.00
		flash_ctrl_csr_aliasing	1.050m	2.536ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	37.590s	2.315ms	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.410s	177.280us	5	5	100.00
		flash_ctrl_csr_rw	18.300s	797.349us	20	20	100.00
		flash_ctrl_csr_aliasing	1.050m	2.536ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	37.590s	2.315ms	20	20	100.00
V2		TOTAL			1013	1013	100.00
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.370s	46.011us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.370s	46.011us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.370s	46.011us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.370s	46.011us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.020s	13.452us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.379h	2.450ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.332m	1.384ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.332m	1.384ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.332m	1.384ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.490s	208.230us	3	3	100.00
		flash_ctrl_wr_intg	15.450s	376.653us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.307m	1.413ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.298m	38.646us	80	80	100.00
		flash_ctrl_disable	22.710s	12.955us	50	50	100.00
		flash_ctrl_sec_info_access	1.374m	7.969ms	50	50	100.00
		flash_ctrl_connect	16.370s	30.393us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.070s	34.275us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.300s	797.349us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.370s	46.011us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.300s	797.349us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.370s	46.011us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.300s	797.349us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.370s	46.011us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.710s	12.955us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.490s	208.230us	3	3	100.00
		flash_ctrl_access_after_disable	13.920s	39.287us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.710s	12.955us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	29.810s	415.959us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.212m	3.629ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	11.670m	22.509ms	10	10	100.00
		flash_ctrl_rw_derr	10.711m	13.489ms	10	10	100.00
		flash_ctrl_integrity	13.617m	91.020ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	33.324m	125.677ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.379h	2.450ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.379h	2.450ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.379h	2.450ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.379h	2.450ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	1.123m	884.608us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.510s	26.565us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.920s	23.562us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.379h	2.450ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.379h	2.450ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.379h	2.450ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	44.400s	46.037us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1278	1278	100.00

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	55	100.00
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.60	95.77	94.18	98.95	92.52	98.26	98.30	98.24

Past Results

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