FLASH_CTRL Simulation Results

Sunday March 10 2024 19:02:34 UTC

GitHub Revision: 8d1fda3660

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 55344925760588090643748974780216117977546302496149780891974223483299136808506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.672m	166.650us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.360s	28.347us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	45.860s	247.191us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.530s	267.080us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.162m	2.480ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	38.650s	813.234us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.090s	149.411us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.530s	267.080us	20	20	100.00
		flash_ctrl_csr_aliasing	38.650s	813.234us	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.460s	15.363us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.880s	58.824us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.760s	20.339us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.346m	45.944us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	31.732m	117.771ms	3	3	100.00
		flash_ctrl_hw_rma_reset	18.328m	320.276ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.840s	14.943us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	46.511m	257.082ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.072m	5.763ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	5.413m	4.071ms	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.254h	49.894ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.313m	732.031us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	36.740s	192.002us	40	40	100.00
		flash_ctrl_rw_evict_all_en	39.110s	686.246us	39	40	97.50
		flash_ctrl_re_evict	39.190s	131.696us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.229m	1.458ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.229m	1.458ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	20.236m	19.423ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	27.690s	465.599us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	24.226m	8.798ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	41.131m	19.538ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.240m	528.960us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	50.571m	1.801ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.850s	24.923us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	2.581m	3.964ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.300s	17.457us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.190s	22.269us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	28.171m	3.725ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.603m	30.275ms	50	50	100.00
		flash_ctrl_otp_reset	2.293m	39.737us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	31.732m	117.771ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.606m	20.523ms	40	40	100.00
		flash_ctrl_intr_wr	1.984m	33.105ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	5.823m	9.076ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	7.678m	104.698ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.682m	32.923ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.234m	9.192ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.670s	24.784us	5	5	100.00
		flash_ctrl_ro_derr	2.356m	667.017us	10	10	100.00
		flash_ctrl_rw_derr	10.744m	15.365ms	10	10	100.00
		flash_ctrl_derr_detect	1.761m	285.728us	5	5	100.00
		flash_ctrl_integrity	8.844m	7.029ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.450s	24.619us	5	5	100.00
		flash_ctrl_ro_serr	2.234m	5.680ms	10	10	100.00
		flash_ctrl_rw_serr	9.877m	60.746ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.304m	1.822ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.342m	9.897ms	5	5	100.00
V2	scramble	flash_ctrl_wo	3.148m	2.308ms	20	20	100.00
		flash_ctrl_write_word_sweep	16.350s	212.508us	1	1	100.00
		flash_ctrl_read_word_sweep	13.240s	14.553us	1	1	100.00
		flash_ctrl_ro	1.858m	2.587ms	20	20	100.00
		flash_ctrl_rw	10.355m	7.197ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	34.210s	1.056ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	15.278m	166.566ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.112m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.920s	188.400us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.220s	28.261us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.340s	98.677us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.340s	98.677us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	45.860s	247.191us	5	5	100.00
		flash_ctrl_csr_rw	17.530s	267.080us	20	20	100.00
		flash_ctrl_csr_aliasing	38.650s	813.234us	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.430s	874.607us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	45.860s	247.191us	5	5	100.00
		flash_ctrl_csr_rw	17.530s	267.080us	20	20	100.00
		flash_ctrl_csr_aliasing	38.650s	813.234us	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.430s	874.607us	20	20	100.00
V2		TOTAL			1012	1013	99.90
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	15.780s	14.388us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	15.780s	14.388us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	15.780s	14.388us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	15.780s	14.388us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	15.980s	13.198us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.334h	2.471ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.354m	13.218ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.354m	13.218ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.354m	13.218ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	31.670s	63.215us	3	3	100.00
		flash_ctrl_wr_intg	14.730s	221.149us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.672m	166.650us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.293m	39.737us	80	80	100.00
		flash_ctrl_disable	22.300s	17.457us	50	50	100.00
		flash_ctrl_sec_info_access	1.588m	8.150ms	50	50	100.00
		flash_ctrl_connect	16.190s	22.269us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	13.810s	22.388us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.530s	267.080us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.780s	14.388us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.530s	267.080us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	15.780s	14.388us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.530s	267.080us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	15.780s	14.388us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.300s	17.457us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	31.670s	63.215us	3	3	100.00
		flash_ctrl_access_after_disable	13.820s	14.256us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.300s	17.457us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	27.690s	465.599us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.355m	7.197ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	9.877m	60.746ms	10	10	100.00
		flash_ctrl_rw_derr	10.744m	15.365ms	10	10	100.00
		flash_ctrl_integrity	8.844m	7.029ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	31.732m	117.771ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.334h	2.471ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.334h	2.471ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.334h	2.471ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.334h	2.471ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	40.250s	826.614us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.100s	99.267us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.030s	25.712us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.334h	2.471ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.334h	2.471ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.334h	2.471ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	42.210s	129.866us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1277	1278	99.92

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	54	98.18
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.62	95.75	94.21	98.95	92.52	98.24	98.41	98.24

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
  • Test flash_ctrl_rw_evict_all_en has 1 failures.

    • 13.flash_ctrl_rw_evict_all_en.52886085174083242672657785817412976546183804728939623958173211047842293105645
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict_all_en/latest/run.log

        UVM_ERROR @ 37242.2 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 37242.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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