FLASH_CTRL Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: bc285b7382

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.679m	23.138us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	27.250s	53.150us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.090s	815.909us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.720s	265.045us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.982m	38.322ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.100m	4.163ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.580s	179.690us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.720s	265.045us	20	20	100.00
		flash_ctrl_csr_aliasing	1.100m	4.163ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.910s	248.642us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.240s	18.680us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.910s	90.936us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.718m	388.631us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	26.769m	167.226ms	2	3	66.67
		flash_ctrl_hw_rma_reset	22.268m	630.325ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.240s	211.396us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	45.043m	247.622ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	7.263m	2.049ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	22.220s	469.547us	30	30	100.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.200h	203.476ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.578m	1.412ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	34.950s	48.778us	37	40	92.50
		flash_ctrl_rw_evict_all_en	38.030s	371.822us	40	40	100.00
		flash_ctrl_re_evict	40.870s	370.201us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.506m	34.064ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.506m	34.064ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	20.932m	65.214ms	19	20	95.00
V2	fetch_code	flash_ctrl_fetch_code	26.070s	154.302us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	25.037m	9.718ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	45.710m	27.904ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.433m	3.584ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	47.224m	2.073ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.290s	46.777us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	4.009m	5.637ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.260s	48.742us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.670s	78.042us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	23.226m	227.907us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.471m	18.887ms	50	50	100.00
		flash_ctrl_otp_reset	2.343m	37.580us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	26.769m	167.226ms	2	3	66.67
V2	interrupts	flash_ctrl_intr_rd	3.992m	1.367ms	40	40	100.00
		flash_ctrl_intr_wr	1.968m	20.438ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	5.710m	17.442ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	8.734m	470.121ms	10	10	100.00
V2	invalid_op	flash_ctrl_invalid_op	1.646m	3.926ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.299m	674.674us	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.280s	34.006us	5	5	100.00
		flash_ctrl_ro_derr	2.953m	1.267ms	10	10	100.00
		flash_ctrl_rw_derr	13.252m	7.851ms	10	10	100.00
		flash_ctrl_derr_detect	1.796m	274.795us	5	5	100.00
		flash_ctrl_integrity	12.515m	31.486ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.620s	26.213us	5	5	100.00
		flash_ctrl_ro_serr	2.939m	2.829ms	10	10	100.00
		flash_ctrl_rw_serr	13.033m	38.950ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.506m	1.533ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.577m	823.170us	5	5	100.00
V2	scramble	flash_ctrl_wo	3.874m	27.423ms	20	20	100.00
		flash_ctrl_write_word_sweep	19.270s	240.666us	1	1	100.00
		flash_ctrl_read_word_sweep	14.460s	99.492us	1	1	100.00
		flash_ctrl_ro	2.340m	1.137ms	20	20	100.00
		flash_ctrl_rw	11.250m	15.649ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	40.100s	610.132us	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	19.923m	92.280ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	4.893m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.560s	40.935us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.090s	44.853us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.260s	61.529us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.260s	61.529us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.090s	815.909us	5	5	100.00
		flash_ctrl_csr_rw	17.720s	265.045us	20	20	100.00
		flash_ctrl_csr_aliasing	1.100m	4.163ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.200s	217.238us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.090s	815.909us	5	5	100.00
		flash_ctrl_csr_rw	17.720s	265.045us	20	20	100.00
		flash_ctrl_csr_aliasing	1.100m	4.163ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.200s	217.238us	20	20	100.00
V2		TOTAL			1008	1013	99.51
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.430s	16.478us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.430s	16.478us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.430s	16.478us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.430s	16.478us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.100s	18.143us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.339h	1.943ms	5	5	100.00
		flash_ctrl_tl_intg_err	15.059m	7.360ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.059m	7.360ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.059m	7.360ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.930s	223.140us	3	3	100.00
		flash_ctrl_wr_intg	15.010s	174.453us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.679m	23.138us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.343m	37.580us	80	80	100.00
		flash_ctrl_disable	23.260s	48.742us	50	50	100.00
		flash_ctrl_sec_info_access	1.438m	9.288ms	50	50	100.00
		flash_ctrl_connect	16.670s	78.042us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.050s	164.610us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.720s	265.045us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.430s	16.478us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.720s	265.045us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.430s	16.478us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.720s	265.045us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.430s	16.478us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.260s	48.742us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.930s	223.140us	3	3	100.00
		flash_ctrl_access_after_disable	14.230s	39.309us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.260s	48.742us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	26.070s	154.302us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.250m	15.649ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	13.033m	38.950ms	10	10	100.00
		flash_ctrl_rw_derr	13.252m	7.851ms	10	10	100.00
		flash_ctrl_integrity	12.515m	31.486ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	26.769m	167.226ms	2	3	66.67
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.339h	1.943ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.339h	1.943ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.339h	1.943ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.339h	1.943ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	1.423m	884.389us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.110s	24.422us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	15.270s	80.882us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.339h	1.943ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.339h	1.943ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.339h	1.943ms	5	5	100.00
V2S		TOTAL			144	144	100.00
V3	asymmetric_read_path	flash_ctrl_rd_ooo	43.620s	511.592us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1273	1278	99.61

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	52	94.55
V2S	12	12	12	100.00
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.31	95.23	94.07	98.95	92.52	96.99	98.41	98.03

Failure Buckets

• UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 3 failures:

  • Test flash_ctrl_rw_evict has 3 failures.

    • 2.flash_ctrl_rw_evict.89535938645150932747206181930674512742825403342435064692276476838305479659867
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 51921.0 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 51921.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.flash_ctrl_rw_evict.38364642899647875120215026177194515254473275190339517309929881180853841086744
      Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict/latest/run.log

        UVM_ERROR @ 10328.7 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
        UVM_INFO @ 10328.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• Offending '$fell(src_ack_o)' has 1 failures:

  • Test flash_ctrl_hw_rma has 1 failures.

    • 1.flash_ctrl_hw_rma.112932388470931820140707772406453442709034552503682497329155610288650905257788
      Line 357, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma/latest/run.log

            Offending '$fell(src_ack_o)'
        UVM_ERROR @ 177069270.1 ns: (prim_sync_reqack.sv:349) [ASSERT FAILED] SyncReqAckHoldReq
        UVM_INFO @ 177069270.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (flash_ctrl_mp_regions_vseq.sv:196) [flash_ctrl_mp_regions_vseq] wait timeout for alert_count == exp_alertcnt after do_mp_reg() alert_cnt:* exp_alert_cnt:* has 1 failures:

  • Test flash_ctrl_mp_regions has 1 failures.

    • 4.flash_ctrl_mp_regions.92582126646855195253922013769683533843867154857817884961469945030958455657247
      Line 687, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_mp_regions/latest/run.log

        UVM_FATAL @ 1550689.5 ns: (flash_ctrl_mp_regions_vseq.sv:196) [uvm_test_top.env.virtual_sequencer.flash_ctrl_mp_regions_vseq] wait timeout for alert_count == exp_alertcnt after do_mp_reg() alert_cnt:21  exp_alert_cnt:22
        UVM_INFO @ 1550689.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
• lint
• 2024.03.11_03.14.12
• 2024.03.08_05.05.27
• 2024.03.06_08.05.24
• 2024.03.04_04.50.55
• 2024.03.01_07.55.19
• 2024.02.29_12.14.44