FLASH_CTRL Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: ae68723071

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke flash_ctrl_smoke 4.197m 13.753ms 50 50 100.00
V1 smoke_hw flash_ctrl_smoke_hw 26.180s 32.359us 5 5 100.00
V1 csr_hw_reset flash_ctrl_csr_hw_reset 46.160s 634.962us 5 5 100.00
V1 csr_rw flash_ctrl_csr_rw 17.610s 200.316us 20 20 100.00
V1 csr_bit_bash flash_ctrl_csr_bit_bash 1.226m 3.677ms 5 5 100.00
V1 csr_aliasing flash_ctrl_csr_aliasing 1.153m 1.722ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset flash_ctrl_csr_mem_rw_with_rand_reset 18.870s 85.861us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr flash_ctrl_csr_rw 17.610s 200.316us 20 20 100.00
flash_ctrl_csr_aliasing 1.153m 1.722ms 5 5 100.00
V1 mem_walk flash_ctrl_mem_walk 13.670s 58.843us 5 5 100.00
V1 mem_partial_access flash_ctrl_mem_partial_access 13.980s 62.292us 5 5 100.00
V1 TOTAL 120 120 100.00
V2 sw_op flash_ctrl_sw_op 26.950s 194.760us 5 5 100.00
V2 host_read_direct flash_ctrl_host_dir_rd 1.881m 66.466us 5 5 100.00
V2 rma_hw_if flash_ctrl_hw_rma 31.775m 334.248ms 3 3 100.00
flash_ctrl_hw_rma_reset 17.884m 540.369ms 20 20 100.00
flash_ctrl_lcmgr_intg 13.740s 46.257us 20 20 100.00
V2 host_controller_arb flash_ctrl_host_ctrl_arb 49.248m 255.216ms 5 5 100.00
V2 erase_suspend flash_ctrl_erase_suspend 8.330m 17.965ms 5 5 100.00
V2 program_reset flash_ctrl_prog_reset 15.760s 224.707us 4 30 13.33
V2 full_memory_access flash_ctrl_full_mem_access 1.197h 48.915ms 5 5 100.00
V2 rd_buff_eviction flash_ctrl_rd_buff_evict 1.700m 74.036us 5 5 100.00
V2 rd_buff_eviction_w_ecc flash_ctrl_rw_evict 32.230s 68.864us 5 40 12.50
flash_ctrl_rw_evict_all_en 32.480s 168.061us 11 40 27.50
flash_ctrl_re_evict 39.580s 139.324us 20 20 100.00
V2 host_arb flash_ctrl_phy_arb 9.099m 1.445ms 20 20 100.00
V2 host_interleave flash_ctrl_phy_arb 9.099m 1.445ms 20 20 100.00
V2 memory_protection flash_ctrl_mp_regions 20.467m 30.172ms 20 20 100.00
V2 fetch_code flash_ctrl_fetch_code 27.530s 1.039ms 10 10 100.00
V2 all_partitions flash_ctrl_rand_ops 20.320m 4.320ms 20 20 100.00
V2 error_mp flash_ctrl_error_mp 42.113m 4.451ms 10 10 100.00
V2 error_prog_win flash_ctrl_error_prog_win 18.014m 4.455ms 10 10 100.00
V2 error_prog_type flash_ctrl_error_prog_type 47.822m 767.882us 5 5 100.00
V2 error_read_seed flash_ctrl_hw_read_seed_err 13.820s 15.345us 20 20 100.00
V2 read_write_overflow flash_ctrl_oversize_error 30.270s 61.924us 0 5 0.00
V2 flash_ctrl_disable flash_ctrl_disable 22.630s 39.006us 38 50 76.00
V2 flash_ctrl_connect flash_ctrl_connect 16.360s 23.943us 80 80 100.00
V2 stress_all flash_ctrl_stress_all 30.867m 2.009ms 5 5 100.00
V2 secret_partition flash_ctrl_hw_sec_otp 4.220m 6.420ms 50 50 100.00
flash_ctrl_otp_reset 2.277m 142.144us 80 80 100.00
V2 isolation_partition flash_ctrl_hw_rma 31.775m 334.248ms 3 3 100.00
V2 interrupts flash_ctrl_intr_rd 3.906m 4.380ms 40 40 100.00
flash_ctrl_intr_wr 14.470s 62.340us 0 10 0.00
flash_ctrl_intr_rd_slow_flash 8.328m 128.971ms 40 40 100.00
flash_ctrl_intr_wr_slow_flash 25.570s 1.835ms 0 10 0.00
V2 invalid_op flash_ctrl_invalid_op 1.564m 967.923us 20 20 100.00
V2 mid_op_rst flash_ctrl_mid_op_rst 1.283m 2.687ms 5 5 100.00
V2 double_bit_err flash_ctrl_read_word_sweep_derr 23.410s 62.566us 5 5 100.00
flash_ctrl_ro_derr 3.142m 2.901ms 10 10 100.00
flash_ctrl_rw_derr 5.063m 5.507ms 0 10 0.00
flash_ctrl_derr_detect 1.643m 143.223us 1 5 20.00
flash_ctrl_integrity 5.340m 10.941ms 0 5 0.00
V2 single_bit_err flash_ctrl_read_word_sweep_serr 23.270s 296.656us 5 5 100.00
flash_ctrl_ro_serr 2.697m 3.972ms 10 10 100.00
flash_ctrl_rw_serr 2.817m 3.091ms 0 10 0.00
V2 singlebit_err_counter flash_ctrl_serr_counter 1.236m 1.224ms 1 5 20.00
V2 singlebit_err_address flash_ctrl_serr_address 1.282m 6.311ms 1 5 20.00
V2 scramble flash_ctrl_wo 4.245m 3.349ms 20 20 100.00
flash_ctrl_write_word_sweep 13.220s 44.246us 0 1 0.00
flash_ctrl_read_word_sweep 14.350s 79.972us 1 1 100.00
flash_ctrl_ro 2.427m 1.356ms 19 20 95.00
flash_ctrl_rw 13.026m 5.524ms 20 20 100.00
V2 filesystem_support flash_ctrl_fs_sup 37.020s 579.090us 2 5 40.00
V2 rma_write_process_error flash_ctrl_rma_err 15.779m 135.563ms 3 3 100.00
flash_ctrl_hw_prog_rma_wipe_err 5.108m 10.013ms 20 20 100.00
V2 alert_test flash_ctrl_alert_test 14.360s 196.047us 50 50 100.00
V2 intr_test flash_ctrl_intr_test 13.890s 42.207us 50 50 100.00
V2 tl_d_oob_addr_access flash_ctrl_tl_errors 19.730s 135.288us 20 20 100.00
V2 tl_d_illegal_access flash_ctrl_tl_errors 19.730s 135.288us 20 20 100.00
V2 tl_d_outstanding_access flash_ctrl_csr_hw_reset 46.160s 634.962us 5 5 100.00
flash_ctrl_csr_rw 17.610s 200.316us 20 20 100.00
flash_ctrl_csr_aliasing 1.153m 1.722ms 5 5 100.00
flash_ctrl_same_csr_outstanding 33.990s 94.720us 20 20 100.00
V2 tl_d_partial_access flash_ctrl_csr_hw_reset 46.160s 634.962us 5 5 100.00
flash_ctrl_csr_rw 17.610s 200.316us 20 20 100.00
flash_ctrl_csr_aliasing 1.153m 1.722ms 5 5 100.00
flash_ctrl_same_csr_outstanding 33.990s 94.720us 20 20 100.00
V2 TOTAL 844 1013 83.32
V2S shadow_reg_update_error flash_ctrl_shadow_reg_errors 16.140s 11.809us 20 20 100.00
V2S shadow_reg_read_clear_staged_value flash_ctrl_shadow_reg_errors 16.140s 11.809us 20 20 100.00
V2S shadow_reg_storage_error flash_ctrl_shadow_reg_errors 16.140s 11.809us 20 20 100.00
V2S shadowed_reset_glitch flash_ctrl_shadow_reg_errors 16.140s 11.809us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw flash_ctrl_shadow_reg_errors_with_csr_rw 16.150s 12.588us 20 20 100.00
V2S tl_intg_err flash_ctrl_sec_cm 38.260s 11.983us 0 5 0.00
flash_ctrl_tl_intg_err 15.717m 11.221ms 20 20 100.00
V2S sec_cm_reg_bus_integrity flash_ctrl_tl_intg_err 15.717m 11.221ms 20 20 100.00
V2S sec_cm_host_bus_integrity flash_ctrl_tl_intg_err 15.717m 11.221ms 20 20 100.00
V2S sec_cm_mem_bus_integrity flash_ctrl_rd_intg 32.260s 268.816us 3 3 100.00
flash_ctrl_wr_intg 14.820s 176.822us 3 3 100.00
V2S sec_cm_scramble_key_sideload flash_ctrl_smoke 4.197m 13.753ms 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi flash_ctrl_otp_reset 2.277m 142.144us 80 80 100.00
flash_ctrl_disable 22.630s 39.006us 38 50 76.00
flash_ctrl_sec_info_access 1.422m 29.060ms 50 50 100.00
flash_ctrl_connect 16.360s 23.943us 80 80 100.00
V2S sec_cm_ctrl_config_regwen flash_ctrl_config_regwen 14.170s 295.860us 5 5 100.00
V2S sec_cm_data_regions_config_regwen flash_ctrl_csr_rw 17.610s 200.316us 20 20 100.00
V2S sec_cm_data_regions_config_shadow flash_ctrl_shadow_reg_errors 16.140s 11.809us 20 20 100.00
V2S sec_cm_info_regions_config_regwen flash_ctrl_csr_rw 17.610s 200.316us 20 20 100.00
V2S sec_cm_info_regions_config_shadow flash_ctrl_shadow_reg_errors 16.140s 11.809us 20 20 100.00
V2S sec_cm_bank_config_regwen flash_ctrl_csr_rw 17.610s 200.316us 20 20 100.00
V2S sec_cm_bank_config_shadow flash_ctrl_shadow_reg_errors 16.140s 11.809us 20 20 100.00
V2S sec_cm_mem_ctrl_global_esc flash_ctrl_disable 22.630s 39.006us 38 50 76.00
V2S sec_cm_mem_ctrl_local_esc flash_ctrl_rd_intg 32.260s 268.816us 3 3 100.00
flash_ctrl_access_after_disable 13.390s 33.786us 0 3 0.00
V2S sec_cm_mem_disable_config_mubi flash_ctrl_disable 22.630s 39.006us 38 50 76.00
V2S sec_cm_exec_config_redun flash_ctrl_fetch_code 27.530s 1.039ms 10 10 100.00
V2S sec_cm_mem_scramble flash_ctrl_rw 13.026m 5.524ms 20 20 100.00
V2S sec_cm_mem_integrity flash_ctrl_rw_serr 2.817m 3.091ms 0 10 0.00
flash_ctrl_rw_derr 5.063m 5.507ms 0 10 0.00
flash_ctrl_integrity 5.340m 10.941ms 0 5 0.00
V2S sec_cm_rma_entry_mem_sec_wipe flash_ctrl_hw_rma 31.775m 334.248ms 3 3 100.00
V2S sec_cm_ctrl_fsm_sparse flash_ctrl_sec_cm 38.260s 11.983us 0 5 0.00
V2S sec_cm_phy_fsm_sparse flash_ctrl_sec_cm 38.260s 11.983us 0 5 0.00
V2S sec_cm_phy_prog_fsm_sparse flash_ctrl_sec_cm 38.260s 11.983us 0 5 0.00
V2S sec_cm_ctr_redun flash_ctrl_sec_cm 38.260s 11.983us 0 5 0.00
V2S sec_cm_phy_arbiter_ctrl_redun flash_ctrl_phy_arb_redun 19.040s 866.073us 5 5 100.00
V2S sec_cm_phy_host_grant_ctrl_consistency flash_ctrl_phy_host_grant_err 14.410s 25.479us 5 5 100.00
V2S sec_cm_phy_ack_ctrl_consistency flash_ctrl_phy_ack_consistency 14.300s 24.870us 5 5 100.00
V2S sec_cm_fifo_ctr_redun flash_ctrl_sec_cm 38.260s 11.983us 0 5 0.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse flash_ctrl_sec_cm 38.260s 11.983us 0 5 0.00
V2S sec_cm_prog_tl_lc_gate_fsm_sparse flash_ctrl_sec_cm 38.260s 11.983us 0 5 0.00
V2S TOTAL 136 144 94.44
V3 asymmetric_read_path flash_ctrl_rd_ooo 45.470s 56.099us 1 1 100.00
V3 stress_all_with_rand_reset flash_ctrl_stress_all_with_rand_reset 0 0 --
V3 TOTAL 1 1 100.00
TOTAL 1101 1278 86.15

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 55 55 39 70.91
V2S 12 12 10 83.33
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.05 95.85 93.23 94.81 91.16 98.07 94.61 97.60

Failure Buckets

Past Results