FLASH_CTRL Simulation Results

Sunday April 28 2024 19:02:25 UTC

GitHub Revision: `ae68723071`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 39039922970915743742128251849028328647614073777998354662703170901147801110391

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.197m	13.753ms	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.180s	32.359us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.160s	634.962us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.610s	200.316us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.226m	3.677ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.153m	1.722ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	18.870s	85.861us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.610s	200.316us	20	20	100.00
		flash_ctrl_csr_aliasing	1.153m	1.722ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.670s	58.843us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.980s	62.292us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.950s	194.760us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.881m	66.466us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	31.775m	334.248ms	3	3	100.00
		flash_ctrl_hw_rma_reset	17.884m	540.369ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.740s	46.257us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	49.248m	255.216ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.330m	17.965ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	15.760s	224.707us	4	30	13.33
V2	full_memory_access	flash_ctrl_full_mem_access	1.197h	48.915ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	1.700m	74.036us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.230s	68.864us	5	40	12.50
		flash_ctrl_rw_evict_all_en	32.480s	168.061us	11	40	27.50
		flash_ctrl_re_evict	39.580s	139.324us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.099m	1.445ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.099m	1.445ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	20.467m	30.172ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	27.530s	1.039ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	20.320m	4.320ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	42.113m	4.451ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	18.014m	4.455ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	47.822m	767.882us	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.820s	15.345us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	30.270s	61.924us	0	5	0.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.630s	39.006us	38	50	76.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.360s	23.943us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	30.867m	2.009ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.220m	6.420ms	50	50	100.00
		flash_ctrl_otp_reset	2.277m	142.144us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	31.775m	334.248ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.906m	4.380ms	40	40	100.00
		flash_ctrl_intr_wr	14.470s	62.340us	0	10	0.00
		flash_ctrl_intr_rd_slow_flash	8.328m	128.971ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	25.570s	1.835ms	0	10	0.00
V2	invalid_op	flash_ctrl_invalid_op	1.564m	967.923us	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.283m	2.687ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.410s	62.566us	5	5	100.00
		flash_ctrl_ro_derr	3.142m	2.901ms	10	10	100.00
		flash_ctrl_rw_derr	5.063m	5.507ms	0	10	0.00
		flash_ctrl_derr_detect	1.643m	143.223us	1	5	20.00
		flash_ctrl_integrity	5.340m	10.941ms	0	5	0.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.270s	296.656us	5	5	100.00
		flash_ctrl_ro_serr	2.697m	3.972ms	10	10	100.00
		flash_ctrl_rw_serr	2.817m	3.091ms	0	10	0.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.236m	1.224ms	1	5	20.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.282m	6.311ms	1	5	20.00
V2	scramble	flash_ctrl_wo	4.245m	3.349ms	20	20	100.00
		flash_ctrl_write_word_sweep	13.220s	44.246us	0	1	0.00
		flash_ctrl_read_word_sweep	14.350s	79.972us	1	1	100.00
		flash_ctrl_ro	2.427m	1.356ms	19	20	95.00
		flash_ctrl_rw	13.026m	5.524ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	37.020s	579.090us	2	5	40.00
V2	rma_write_process_error	flash_ctrl_rma_err	15.779m	135.563ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.108m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.360s	196.047us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	13.890s	42.207us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.730s	135.288us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.730s	135.288us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.160s	634.962us	5	5	100.00
		flash_ctrl_csr_rw	17.610s	200.316us	20	20	100.00
		flash_ctrl_csr_aliasing	1.153m	1.722ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	33.990s	94.720us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.160s	634.962us	5	5	100.00
		flash_ctrl_csr_rw	17.610s	200.316us	20	20	100.00
		flash_ctrl_csr_aliasing	1.153m	1.722ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	33.990s	94.720us	20	20	100.00
V2		TOTAL			844	1013	83.32
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.140s	11.809us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.140s	11.809us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.140s	11.809us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.140s	11.809us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.150s	12.588us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	38.260s	11.983us	0	5	0.00
		flash_ctrl_tl_intg_err	15.717m	11.221ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.717m	11.221ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.717m	11.221ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.260s	268.816us	3	3	100.00
		flash_ctrl_wr_intg	14.820s	176.822us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.197m	13.753ms	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.277m	142.144us	80	80	100.00
		flash_ctrl_disable	22.630s	39.006us	38	50	76.00
		flash_ctrl_sec_info_access	1.422m	29.060ms	50	50	100.00
		flash_ctrl_connect	16.360s	23.943us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.170s	295.860us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.610s	200.316us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.140s	11.809us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.610s	200.316us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.140s	11.809us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.610s	200.316us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.140s	11.809us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.630s	39.006us	38	50	76.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.260s	268.816us	3	3	100.00
		flash_ctrl_access_after_disable	13.390s	33.786us	0	3	0.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.630s	39.006us	38	50	76.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	27.530s	1.039ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	13.026m	5.524ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	2.817m	3.091ms	0	10	0.00
		flash_ctrl_rw_derr	5.063m	5.507ms	0	10	0.00
		flash_ctrl_integrity	5.340m	10.941ms	0	5	0.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	31.775m	334.248ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	38.260s	11.983us	0	5	0.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	38.260s	11.983us	0	5	0.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	38.260s	11.983us	0	5	0.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	38.260s	11.983us	0	5	0.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	19.040s	866.073us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.410s	25.479us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.300s	24.870us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	38.260s	11.983us	0	5	0.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	38.260s	11.983us	0	5	0.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	38.260s	11.983us	0	5	0.00
V2S		TOTAL			136	144	94.44
V3	asymmetric_read_path	flash_ctrl_rd_ooo	45.470s	56.099us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1101	1278	86.15

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	39	70.91
V2S	12	12	10	83.33
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.05	95.85	93.23	94.81	91.16	98.07	94.61	97.60

Failure Buckets

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 38 failures:

Test flash_ctrl_rw_evict_all_en has 18 failures.

1.flash_ctrl_rw_evict_all_en.30136074020833931292189719184649622545517771564292558997075369861832705386322
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 11380.4 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 11380.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_rw_evict_all_en.8381492666953093831291904636256156217081038109501020557460829682562929010986
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 43382.7 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 43382.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 16 more failures.

Test flash_ctrl_rw_evict has 20 failures.

2.flash_ctrl_rw_evict.5325242833302879425579181901892290780094943112019850189585402924030212219664
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 16711.7 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 16711.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.flash_ctrl_rw_evict.36533479481473698049654986229014158619841439619854349972137805054833481269235
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 41230.6 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 41230.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 18 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 25 failures:

Test flash_ctrl_rw_serr has 10 failures.

0.flash_ctrl_rw_serr.39466124504992591740750535631820695352811512664996381615174622759338938285774
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest/run.log

  UVM_FATAL @ 266280.6 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00004678
  UVM_INFO @ 266280.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_rw_serr.94275047633691279547171429397005013150955193930468853743396227514810931182002
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log

  UVM_FATAL @ 259710.4 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00004c78
  UVM_INFO @ 259710.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test flash_ctrl_rw_derr has 10 failures.

0.flash_ctrl_rw_derr.40070431051883459160749872766345281552519595295972971808319943383093476085111
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest/run.log

  UVM_FATAL @ 3549492.8 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x0006cca8
  UVM_INFO @ 3549492.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_rw_derr.89138491435290977840409809047955083148383214587285482015378434475820752360244
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log

  UVM_FATAL @ 5506827.8 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00004af8
  UVM_INFO @ 5506827.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test flash_ctrl_integrity has 5 failures.

0.flash_ctrl_integrity.31108864106967505475056843514252495391122401428361615208386002543747790026261
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log

  UVM_FATAL @ 5819541.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00003650
  UVM_INFO @ 5819541.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_integrity.99037330052608245450283897450307733462314917832762227110991075361434674814030
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log

  UVM_FATAL @ 10940871.8 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000800
  UVM_INFO @ 10940871.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_rw_evict_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 21 failures:

Test flash_ctrl_rw_evict has 12 failures.

0.flash_ctrl_rw_evict.98411051966593930113423029335493299257786747255686629467170292193795002536901
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 20368.6 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 20368.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.flash_ctrl_rw_evict.38839726506070563510764254453771373636450442776901802259070009864660413598954
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 9390.3 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 9390.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

Test flash_ctrl_rw_evict_all_en has 9 failures.

0.flash_ctrl_rw_evict_all_en.11705494574625102011744307083474503774761484670604554465922659854294108981360
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 58861.0 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 58861.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.flash_ctrl_rw_evict_all_en.52227610683549542477105606736155062757835615768187157600077091796481484329745
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 39244.0 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 39244.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 19 failures:

Test flash_ctrl_intr_wr has 9 failures.

0.flash_ctrl_intr_wr.90525598329115584065889616366292408653553147178395463091805270516560048914337
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr/latest/run.log

  UVM_ERROR @ 7415.4 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 7415.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_intr_wr.85088824285791476771802756784934779961323530144132500499770246037786806414864
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr/latest/run.log

  UVM_ERROR @ 4918.9 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 4918.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test flash_ctrl_intr_wr_slow_flash has 10 failures.

0.flash_ctrl_intr_wr_slow_flash.39902251388668575191227180445393215716385982564802564546753959909098126095224
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr_slow_flash/latest/run.log

  UVM_ERROR @ 20703.7 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 20703.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_intr_wr_slow_flash.94362581819412784701917516601803975325621440546154612743197392280719036560719
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr_slow_flash/latest/run.log

  UVM_ERROR @ 138166.0 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 138166.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_prog_reset_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 16 failures:

Test flash_ctrl_prog_reset has 16 failures.

1.flash_ctrl_prog_reset.38907943756623094364634869694177494199709381706410275478081442827231126089671
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_prog_reset/latest/run.log

  UVM_ERROR @ 41141.1 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 41141.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_prog_reset.99368486538149829981339663075413666400986794141341853209863787412625643709689
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_prog_reset/latest/run.log

  UVM_ERROR @ 4549.0 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 4549.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 14 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_prog_reset_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 10 failures:
- Test flash_ctrl_prog_reset has 10 failures.
  - 0.flash_ctrl_prog_reset.19286165286166769984289829411006820491015483624611779894002402205750351717568
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_prog_reset/latest/run.log
```
  UVM_ERROR @ 10953.0 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 10953.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 6.flash_ctrl_prog_reset.61332946838703629638413499183505525104197838532764029727140361761509711220188
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_prog_reset/latest/run.log
```
  UVM_ERROR @ 9599.0 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 9599.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 8 more failures.
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_disable_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 6 failures:
- Test flash_ctrl_disable has 6 failures.
  - 5.flash_ctrl_disable.72030002209247143876365968945764314423311177410026458610859909991626720194076
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_disable/latest/run.log
```
  UVM_ERROR @ 46647.4 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 46647.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 16.flash_ctrl_disable.92332586193902663784218415275729387400169475775867648570370290406932094344170
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_disable/latest/run.log
```
  UVM_ERROR @ 5689.3 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 5689.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_common_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 5 failures:

Test flash_ctrl_sec_cm has 5 failures.

0.flash_ctrl_sec_cm.106217304074038442921049617677884015840085069567855209440448530062518244621744
Line 298, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_sec_cm/latest/run.log

  UVM_ERROR @ 38096.7 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 38096.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_sec_cm.34795085297723601011966922540390045706118944197547398747951451677798550043536
Line 344, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_sec_cm/latest/run.log

  UVM_ERROR @ 11982.9 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 11982.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 5 failures:

Test flash_ctrl_rw_evict has 3 failures.

19.flash_ctrl_rw_evict.31718485929487665645161108435560350556968556738350885151732459061118947219763
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 32051.6 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000d08
  UVM_INFO @ 32051.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

23.flash_ctrl_rw_evict.13446834313637858729740079348048906222532370369984334423006534559182494348328
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 23470.0 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00039650
  UVM_INFO @ 23470.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Test flash_ctrl_rw_evict_all_en has 2 failures.

33.flash_ctrl_rw_evict_all_en.7941188416633287178601884811329701122972854283751994055354769337561180402342
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 17022.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000014e8
  UVM_INFO @ 17022.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

35.flash_ctrl_rw_evict_all_en.42066175756595848696865934998083047667080215444683354711691096061479662311873
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 52703.8 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000860
  UVM_INFO @ 52703.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_serr_address_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 4 failures:
- Test flash_ctrl_serr_address has 4 failures.
  - 0.flash_ctrl_serr_address.9251027390386681572100225874278526735606557514962983048243133432088443137265
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_serr_address/latest/run.log
```
  UVM_FATAL @ 6239503.9 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_address_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000d0868
  UVM_INFO @ 6239503.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.flash_ctrl_serr_address.50841071927231291458593892434283399839864397746635237870279356041582101938830
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_serr_address/latest/run.log
```
  UVM_FATAL @ 192546.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_address_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00003438
  UVM_INFO @ 192546.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_oversize_error_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 4 failures:

Test flash_ctrl_oversize_error has 4 failures.

0.flash_ctrl_oversize_error.27263330297921088802933672590332619507885759199372320974631026173209745210671
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_oversize_error/latest/run.log

  UVM_ERROR @ 4856.3 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_oversize_error_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 4856.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_oversize_error.18072665039547551883912391667224848546616420173644583448798192725764402719588
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_oversize_error/latest/run.log

  UVM_ERROR @ 5783.6 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_oversize_error_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 5783.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_serr_counter_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 4 failures:
- Test flash_ctrl_serr_counter has 4 failures.
  - 1.flash_ctrl_serr_counter.8005408985342334046265607155748879463509124682876677890513295327432124871161
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_serr_counter/latest/run.log
```
  UVM_FATAL @ 195992.7 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_counter_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00004990
  UVM_INFO @ 195992.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.flash_ctrl_serr_counter.64956213218234545019392477187049803254844322955139401783611091709285023209712
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_serr_counter/latest/run.log
```
  UVM_FATAL @ 125477.5 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_counter_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00004e50
  UVM_INFO @ 125477.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_disable_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 4 failures:

Test flash_ctrl_disable has 4 failures.

35.flash_ctrl_disable.84069724848903745151826458423515423883949518795202654780169742054894175268756
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/35.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 11356.3 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 11356.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

37.flash_ctrl_disable.53267879575289717207328495812699109596505181944445202467892343718506390751698
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/37.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 19173.8 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 19173.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_derr_detect_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 3 failures:

Test flash_ctrl_derr_detect has 3 failures.

0.flash_ctrl_derr_detect.112704644378655534910997244302425689218666525513247254718034141205846721445219
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log

  UVM_ERROR @ 19684.4 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_derr_detect_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 19684.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_derr_detect.64598734866718734282977008786689484881171365673472214331985420670832397007976
Line 303, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log

  UVM_ERROR @ 130192.7 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_derr_detect_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 130192.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_access_after_disable_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 3 failures:
- Test flash_ctrl_access_after_disable has 3 failures.
  - 0.flash_ctrl_access_after_disable.51353556468554685562058578080533733402757724714930035280827279277132666688444
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_access_after_disable/latest/run.log
```
  UVM_ERROR @ 11480.0 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_access_after_disable_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 11480.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.flash_ctrl_access_after_disable.44544692781097816343086869110220249992981578221304645070679044946961249503144
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_access_after_disable/latest/run.log
```
  UVM_ERROR @ 5663.3 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_access_after_disable_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 5663.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_filesystem_support_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 3 failures:

Test flash_ctrl_fs_sup has 3 failures.

0.flash_ctrl_fs_sup.67928561828837322432677188031295213168385218917417135995430612878612509739337
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_fs_sup/latest/run.log

  UVM_FATAL @ 5999.4 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_filesystem_support_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000e28
  UVM_INFO @ 5999.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_fs_sup.71024404766804735976967479302039190020212326544542815326130821176035932316896
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_fs_sup/latest/run.log

  UVM_FATAL @ 84763.4 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_filesystem_support_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000aa0
  UVM_INFO @ 84763.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_disable_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 2 failures:
- Test flash_ctrl_disable has 2 failures.
  - 27.flash_ctrl_disable.46721525543545705631083788563222414721496253940422737186491788243689896677433
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_disable/latest/run.log
```
  UVM_FATAL @ 5593.6 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000a48
  UVM_INFO @ 5593.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 40.flash_ctrl_disable.65001566780608756754520885207427671846709671735059892826832172480784113095321
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/40.flash_ctrl_disable/latest/run.log
```
  UVM_FATAL @ 106529.0 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000008d8
  UVM_INFO @ 106529.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_write_word_sweep_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 1 failures:
- Test flash_ctrl_write_word_sweep has 1 failures.
  - 0.flash_ctrl_write_word_sweep.45248056243867455125968512123148226204146249606500500735230885943657341712717
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_write_word_sweep/latest/run.log
```
  UVM_ERROR @ 44246.0 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_write_word_sweep_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 44246.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_derr_detect_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 2.flash_ctrl_derr_detect.100941241691421782069072989675200074308802982971915679644542776354408456896539
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 78979.1 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_derr_detect_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 78979.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_intr_wr_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_intr_wr has 1 failures.
  - 3.flash_ctrl_intr_wr.104811354706927983286033494210950653014192861469359842982971128560960559542174
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr/latest/run.log
```
  UVM_FATAL @ 4719.9 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000800
  UVM_INFO @ 4719.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_oversize_error_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 1 failures:
- Test flash_ctrl_oversize_error has 1 failures.
  - 4.flash_ctrl_oversize_error.47377377095388904890176137186661837526422587859130824275762534218495141314316
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_oversize_error/latest/run.log
```
  UVM_ERROR @ 9737.0 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_oversize_error_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 9737.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_ro has 1 failures.
  - 15.flash_ctrl_ro.81309820113882758255790762632563629555791616700504350903279694431062146143646
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/15.flash_ctrl_ro/latest/run.log
```
  UVM_ERROR @ 330764.4 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 330764.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```