FLASH_CTRL Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: 0cb61fc7e7

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke flash_ctrl_smoke 3.669m 31.661us 50 50 100.00
V1 smoke_hw flash_ctrl_smoke_hw 26.290s 31.885us 5 5 100.00
V1 csr_hw_reset flash_ctrl_csr_hw_reset 47.810s 26.972us 5 5 100.00
V1 csr_rw flash_ctrl_csr_rw 18.420s 915.971us 20 20 100.00
V1 csr_bit_bash flash_ctrl_csr_bit_bash 1.571m 13.103ms 5 5 100.00
V1 csr_aliasing flash_ctrl_csr_aliasing 1.200m 7.511ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset flash_ctrl_csr_mem_rw_with_rand_reset 19.550s 54.098us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr flash_ctrl_csr_rw 18.420s 915.971us 20 20 100.00
flash_ctrl_csr_aliasing 1.200m 7.511ms 5 5 100.00
V1 mem_walk flash_ctrl_mem_walk 13.540s 18.127us 5 5 100.00
V1 mem_partial_access flash_ctrl_mem_partial_access 13.950s 46.535us 5 5 100.00
V1 TOTAL 120 120 100.00
V2 sw_op flash_ctrl_sw_op 27.320s 104.062us 5 5 100.00
V2 host_read_direct flash_ctrl_host_dir_rd 2.050m 76.013us 5 5 100.00
V2 rma_hw_if flash_ctrl_hw_rma 33.917m 334.667ms 3 3 100.00
flash_ctrl_hw_rma_reset 25.045m 760.426ms 20 20 100.00
flash_ctrl_lcmgr_intg 14.620s 15.557us 20 20 100.00
V2 host_controller_arb flash_ctrl_host_ctrl_arb 46.792m 273.371ms 5 5 100.00
V2 erase_suspend flash_ctrl_erase_suspend 7.318m 2.133ms 5 5 100.00
V2 program_reset flash_ctrl_prog_reset 23.980s 802.867us 1 30 3.33
V2 full_memory_access flash_ctrl_full_mem_access 1.123h 48.914ms 5 5 100.00
V2 rd_buff_eviction flash_ctrl_rd_buff_evict 3.447m 1.358ms 5 5 100.00
V2 rd_buff_eviction_w_ecc flash_ctrl_rw_evict 32.490s 10.328us 5 40 12.50
flash_ctrl_rw_evict_all_en 32.460s 41.570us 10 40 25.00
flash_ctrl_re_evict 40.380s 141.415us 20 20 100.00
V2 host_arb flash_ctrl_phy_arb 9.607m 1.393ms 20 20 100.00
V2 host_interleave flash_ctrl_phy_arb 9.607m 1.393ms 20 20 100.00
V2 memory_protection flash_ctrl_mp_regions 17.392m 123.477ms 20 20 100.00
V2 fetch_code flash_ctrl_fetch_code 28.840s 1.449ms 10 10 100.00
V2 all_partitions flash_ctrl_rand_ops 24.678m 8.933ms 20 20 100.00
V2 error_mp flash_ctrl_error_mp 44.569m 26.307ms 10 10 100.00
V2 error_prog_win flash_ctrl_error_prog_win 16.217m 2.393ms 10 10 100.00
V2 error_prog_type flash_ctrl_error_prog_type 51.316m 1.050ms 5 5 100.00
V2 error_read_seed flash_ctrl_hw_read_seed_err 14.330s 19.486us 20 20 100.00
V2 read_write_overflow flash_ctrl_oversize_error 35.620s 134.561us 0 5 0.00
V2 flash_ctrl_disable flash_ctrl_disable 23.200s 93.207us 34 50 68.00
V2 flash_ctrl_connect flash_ctrl_connect 16.480s 16.468us 80 80 100.00
V2 stress_all flash_ctrl_stress_all 26.005m 3.771ms 5 5 100.00
V2 secret_partition flash_ctrl_hw_sec_otp 4.416m 3.169ms 50 50 100.00
flash_ctrl_otp_reset 2.289m 430.778us 80 80 100.00
V2 isolation_partition flash_ctrl_hw_rma 33.917m 334.667ms 3 3 100.00
V2 interrupts flash_ctrl_intr_rd 3.534m 11.156ms 40 40 100.00
flash_ctrl_intr_wr 16.080s 144.876us 0 10 0.00
flash_ctrl_intr_rd_slow_flash 4.533m 55.479ms 40 40 100.00
flash_ctrl_intr_wr_slow_flash 27.330s 6.038ms 0 10 0.00
V2 invalid_op flash_ctrl_invalid_op 1.692m 1.697ms 20 20 100.00
V2 mid_op_rst flash_ctrl_mid_op_rst 1.198m 3.286ms 5 5 100.00
V2 double_bit_err flash_ctrl_read_word_sweep_derr 23.350s 32.041us 5 5 100.00
flash_ctrl_ro_derr 3.073m 955.857us 10 10 100.00
flash_ctrl_rw_derr 5.349m 6.536ms 0 10 0.00
flash_ctrl_derr_detect 1.744m 281.165us 1 5 20.00
flash_ctrl_integrity 3.466m 1.116ms 0 5 0.00
V2 single_bit_err flash_ctrl_read_word_sweep_serr 23.550s 40.105us 5 5 100.00
flash_ctrl_ro_serr 2.856m 788.484us 10 10 100.00
flash_ctrl_rw_serr 3.555m 2.864ms 0 10 0.00
V2 singlebit_err_counter flash_ctrl_serr_counter 1.285m 712.791us 0 5 0.00
V2 singlebit_err_address flash_ctrl_serr_address 1.714m 3.999ms 1 5 20.00
V2 scramble flash_ctrl_wo 4.539m 40.658ms 20 20 100.00
flash_ctrl_write_word_sweep 13.190s 4.747us 0 1 0.00
flash_ctrl_read_word_sweep 14.320s 180.640us 1 1 100.00
flash_ctrl_ro 2.710m 676.679us 20 20 100.00
flash_ctrl_rw 12.665m 58.457ms 19 20 95.00
V2 filesystem_support flash_ctrl_fs_sup 22.810s 530.436us 0 5 0.00
V2 rma_write_process_error flash_ctrl_rma_err 20.127m 73.592ms 3 3 100.00
flash_ctrl_hw_prog_rma_wipe_err 5.535m 10.012ms 20 20 100.00
V2 alert_test flash_ctrl_alert_test 14.950s 90.871us 50 50 100.00
V2 intr_test flash_ctrl_intr_test 14.240s 52.315us 50 50 100.00
V2 tl_d_oob_addr_access flash_ctrl_tl_errors 19.560s 196.175us 20 20 100.00
V2 tl_d_illegal_access flash_ctrl_tl_errors 19.560s 196.175us 20 20 100.00
V2 tl_d_outstanding_access flash_ctrl_csr_hw_reset 47.810s 26.972us 5 5 100.00
flash_ctrl_csr_rw 18.420s 915.971us 20 20 100.00
flash_ctrl_csr_aliasing 1.200m 7.511ms 5 5 100.00
flash_ctrl_same_csr_outstanding 36.620s 211.641us 20 20 100.00
V2 tl_d_partial_access flash_ctrl_csr_hw_reset 47.810s 26.972us 5 5 100.00
flash_ctrl_csr_rw 18.420s 915.971us 20 20 100.00
flash_ctrl_csr_aliasing 1.200m 7.511ms 5 5 100.00
flash_ctrl_same_csr_outstanding 36.620s 211.641us 20 20 100.00
V2 TOTAL 833 1013 82.23
V2S shadow_reg_update_error flash_ctrl_shadow_reg_errors 16.190s 13.331us 20 20 100.00
V2S shadow_reg_read_clear_staged_value flash_ctrl_shadow_reg_errors 16.190s 13.331us 20 20 100.00
V2S shadow_reg_storage_error flash_ctrl_shadow_reg_errors 16.190s 13.331us 20 20 100.00
V2S shadowed_reset_glitch flash_ctrl_shadow_reg_errors 16.190s 13.331us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw flash_ctrl_shadow_reg_errors_with_csr_rw 16.070s 22.644us 20 20 100.00
V2S tl_intg_err flash_ctrl_sec_cm 59.060s 84.314us 0 5 0.00
flash_ctrl_tl_intg_err 15.290m 1.016ms 20 20 100.00
V2S sec_cm_reg_bus_integrity flash_ctrl_tl_intg_err 15.290m 1.016ms 20 20 100.00
V2S sec_cm_host_bus_integrity flash_ctrl_tl_intg_err 15.290m 1.016ms 20 20 100.00
V2S sec_cm_mem_bus_integrity flash_ctrl_rd_intg 33.430s 65.053us 3 3 100.00
flash_ctrl_wr_intg 15.370s 85.822us 3 3 100.00
V2S sec_cm_scramble_key_sideload flash_ctrl_smoke 3.669m 31.661us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi flash_ctrl_otp_reset 2.289m 430.778us 80 80 100.00
flash_ctrl_disable 23.200s 93.207us 34 50 68.00
flash_ctrl_sec_info_access 1.854m 31.654ms 50 50 100.00
flash_ctrl_connect 16.480s 16.468us 80 80 100.00
V2S sec_cm_ctrl_config_regwen flash_ctrl_config_regwen 14.250s 70.134us 5 5 100.00
V2S sec_cm_data_regions_config_regwen flash_ctrl_csr_rw 18.420s 915.971us 20 20 100.00
V2S sec_cm_data_regions_config_shadow flash_ctrl_shadow_reg_errors 16.190s 13.331us 20 20 100.00
V2S sec_cm_info_regions_config_regwen flash_ctrl_csr_rw 18.420s 915.971us 20 20 100.00
V2S sec_cm_info_regions_config_shadow flash_ctrl_shadow_reg_errors 16.190s 13.331us 20 20 100.00
V2S sec_cm_bank_config_regwen flash_ctrl_csr_rw 18.420s 915.971us 20 20 100.00
V2S sec_cm_bank_config_shadow flash_ctrl_shadow_reg_errors 16.190s 13.331us 20 20 100.00
V2S sec_cm_mem_ctrl_global_esc flash_ctrl_disable 23.200s 93.207us 34 50 68.00
V2S sec_cm_mem_ctrl_local_esc flash_ctrl_rd_intg 33.430s 65.053us 3 3 100.00
flash_ctrl_access_after_disable 14.110s 19.539us 0 3 0.00
V2S sec_cm_mem_disable_config_mubi flash_ctrl_disable 23.200s 93.207us 34 50 68.00
V2S sec_cm_exec_config_redun flash_ctrl_fetch_code 28.840s 1.449ms 10 10 100.00
V2S sec_cm_mem_scramble flash_ctrl_rw 12.665m 58.457ms 19 20 95.00
V2S sec_cm_mem_integrity flash_ctrl_rw_serr 3.555m 2.864ms 0 10 0.00
flash_ctrl_rw_derr 5.349m 6.536ms 0 10 0.00
flash_ctrl_integrity 3.466m 1.116ms 0 5 0.00
V2S sec_cm_rma_entry_mem_sec_wipe flash_ctrl_hw_rma 33.917m 334.667ms 3 3 100.00
V2S sec_cm_ctrl_fsm_sparse flash_ctrl_sec_cm 59.060s 84.314us 0 5 0.00
V2S sec_cm_phy_fsm_sparse flash_ctrl_sec_cm 59.060s 84.314us 0 5 0.00
V2S sec_cm_phy_prog_fsm_sparse flash_ctrl_sec_cm 59.060s 84.314us 0 5 0.00
V2S sec_cm_ctr_redun flash_ctrl_sec_cm 59.060s 84.314us 0 5 0.00
V2S sec_cm_phy_arbiter_ctrl_redun flash_ctrl_phy_arb_redun 23.530s 644.555us 5 5 100.00
V2S sec_cm_phy_host_grant_ctrl_consistency flash_ctrl_phy_host_grant_err 14.350s 44.166us 5 5 100.00
V2S sec_cm_phy_ack_ctrl_consistency flash_ctrl_phy_ack_consistency 14.480s 121.153us 5 5 100.00
V2S sec_cm_fifo_ctr_redun flash_ctrl_sec_cm 59.060s 84.314us 0 5 0.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse flash_ctrl_sec_cm 59.060s 84.314us 0 5 0.00
V2S sec_cm_prog_tl_lc_gate_fsm_sparse flash_ctrl_sec_cm 59.060s 84.314us 0 5 0.00
V2S TOTAL 136 144 94.44
V3 asymmetric_read_path flash_ctrl_rd_ooo 47.220s 74.993us 1 1 100.00
V3 stress_all_with_rand_reset flash_ctrl_stress_all_with_rand_reset 0 0 --
V3 TOTAL 1 1 100.00
TOTAL 1090 1278 85.29

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 55 55 39 70.91
V2S 12 12 10 83.33
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.99 95.78 93.24 94.81 90.48 97.84 95.01 97.78

Failure Buckets

Past Results