FLASH_CTRL Simulation Results

Tuesday April 30 2024 19:02:27 UTC

GitHub Revision: `0cb61fc7e7`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 29629349767786988748941369645310183062873507656225682712521573681396210883738

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.669m	31.661us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.290s	31.885us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	47.810s	26.972us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	18.420s	915.971us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.571m	13.103ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.200m	7.511ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.550s	54.098us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	18.420s	915.971us	20	20	100.00
		flash_ctrl_csr_aliasing	1.200m	7.511ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.540s	18.127us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.950s	46.535us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	27.320s	104.062us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.050m	76.013us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	33.917m	334.667ms	3	3	100.00
		flash_ctrl_hw_rma_reset	25.045m	760.426ms	20	20	100.00
		flash_ctrl_lcmgr_intg	14.620s	15.557us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	46.792m	273.371ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	7.318m	2.133ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	23.980s	802.867us	1	30	3.33
V2	full_memory_access	flash_ctrl_full_mem_access	1.123h	48.914ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	3.447m	1.358ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.490s	10.328us	5	40	12.50
		flash_ctrl_rw_evict_all_en	32.460s	41.570us	10	40	25.00
		flash_ctrl_re_evict	40.380s	141.415us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.607m	1.393ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.607m	1.393ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	17.392m	123.477ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	28.840s	1.449ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	24.678m	8.933ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	44.569m	26.307ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	16.217m	2.393ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	51.316m	1.050ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.330s	19.486us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	35.620s	134.561us	0	5	0.00
V2	flash_ctrl_disable	flash_ctrl_disable	23.200s	93.207us	34	50	68.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.480s	16.468us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	26.005m	3.771ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.416m	3.169ms	50	50	100.00
		flash_ctrl_otp_reset	2.289m	430.778us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	33.917m	334.667ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.534m	11.156ms	40	40	100.00
		flash_ctrl_intr_wr	16.080s	144.876us	0	10	0.00
		flash_ctrl_intr_rd_slow_flash	4.533m	55.479ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	27.330s	6.038ms	0	10	0.00
V2	invalid_op	flash_ctrl_invalid_op	1.692m	1.697ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.198m	3.286ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.350s	32.041us	5	5	100.00
		flash_ctrl_ro_derr	3.073m	955.857us	10	10	100.00
		flash_ctrl_rw_derr	5.349m	6.536ms	0	10	0.00
		flash_ctrl_derr_detect	1.744m	281.165us	1	5	20.00
		flash_ctrl_integrity	3.466m	1.116ms	0	5	0.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.550s	40.105us	5	5	100.00
		flash_ctrl_ro_serr	2.856m	788.484us	10	10	100.00
		flash_ctrl_rw_serr	3.555m	2.864ms	0	10	0.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.285m	712.791us	0	5	0.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.714m	3.999ms	1	5	20.00
V2	scramble	flash_ctrl_wo	4.539m	40.658ms	20	20	100.00
		flash_ctrl_write_word_sweep	13.190s	4.747us	0	1	0.00
		flash_ctrl_read_word_sweep	14.320s	180.640us	1	1	100.00
		flash_ctrl_ro	2.710m	676.679us	20	20	100.00
		flash_ctrl_rw	12.665m	58.457ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	22.810s	530.436us	0	5	0.00
V2	rma_write_process_error	flash_ctrl_rma_err	20.127m	73.592ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.535m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.950s	90.871us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.240s	52.315us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	19.560s	196.175us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	19.560s	196.175us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	47.810s	26.972us	5	5	100.00
		flash_ctrl_csr_rw	18.420s	915.971us	20	20	100.00
		flash_ctrl_csr_aliasing	1.200m	7.511ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.620s	211.641us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	47.810s	26.972us	5	5	100.00
		flash_ctrl_csr_rw	18.420s	915.971us	20	20	100.00
		flash_ctrl_csr_aliasing	1.200m	7.511ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	36.620s	211.641us	20	20	100.00
V2		TOTAL			833	1013	82.23
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.190s	13.331us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.190s	13.331us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.190s	13.331us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.190s	13.331us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.070s	22.644us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	59.060s	84.314us	0	5	0.00
		flash_ctrl_tl_intg_err	15.290m	1.016ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.290m	1.016ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.290m	1.016ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	33.430s	65.053us	3	3	100.00
		flash_ctrl_wr_intg	15.370s	85.822us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.669m	31.661us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.289m	430.778us	80	80	100.00
		flash_ctrl_disable	23.200s	93.207us	34	50	68.00
		flash_ctrl_sec_info_access	1.854m	31.654ms	50	50	100.00
		flash_ctrl_connect	16.480s	16.468us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.250s	70.134us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	18.420s	915.971us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.190s	13.331us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	18.420s	915.971us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.190s	13.331us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	18.420s	915.971us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.190s	13.331us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	23.200s	93.207us	34	50	68.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	33.430s	65.053us	3	3	100.00
		flash_ctrl_access_after_disable	14.110s	19.539us	0	3	0.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	23.200s	93.207us	34	50	68.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	28.840s	1.449ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	12.665m	58.457ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	3.555m	2.864ms	0	10	0.00
		flash_ctrl_rw_derr	5.349m	6.536ms	0	10	0.00
		flash_ctrl_integrity	3.466m	1.116ms	0	5	0.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	33.917m	334.667ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	59.060s	84.314us	0	5	0.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	59.060s	84.314us	0	5	0.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	59.060s	84.314us	0	5	0.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	59.060s	84.314us	0	5	0.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	23.530s	644.555us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.350s	44.166us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.480s	121.153us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	59.060s	84.314us	0	5	0.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	59.060s	84.314us	0	5	0.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	59.060s	84.314us	0	5	0.00
V2S		TOTAL			136	144	94.44
V3	asymmetric_read_path	flash_ctrl_rd_ooo	47.220s	74.993us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1090	1278	85.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	39	70.91
V2S	12	12	10	83.33
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.99	95.78	93.24	94.81	90.48	97.84	95.01	97.78

Failure Buckets

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 45 failures:

Test flash_ctrl_rw_evict has 26 failures.

0.flash_ctrl_rw_evict.17150782221020421651214374119559981934953973145195756770232607385827198323152
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 36107.1 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 36107.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_rw_evict.8423342672688368648300503773772215390735021106654741486038461186102072770921
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 10328.2 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 10328.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 24 more failures.

Test flash_ctrl_rw_evict_all_en has 19 failures.

0.flash_ctrl_rw_evict_all_en.36883828644457300745344434270425509407690610303234639970497162190577427031871
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 45931.5 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 45931.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_rw_evict_all_en.20744890687488604307698985142705564272868591855598414360489798992517581770543
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 35299.7 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 35299.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 17 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 25 failures:

Test flash_ctrl_rw_serr has 10 failures.

0.flash_ctrl_rw_serr.34218104899271841251970172315311938166769382203018805034527151670053868367115
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest/run.log

  UVM_FATAL @ 574794.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00002770
  UVM_INFO @ 574794.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_rw_serr.89438221088348151493938066293608753662936453051696423535498403170503350139184
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log

  UVM_FATAL @ 5541593.9 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00002758
  UVM_INFO @ 5541593.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test flash_ctrl_rw_derr has 10 failures.

0.flash_ctrl_rw_derr.96157291498947924777658186815567758085326834279930916993994028491054613396528
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest/run.log

  UVM_FATAL @ 408223.5 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00003db0
  UVM_INFO @ 408223.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_rw_derr.43236356600421745639208078174474668792714721203336304611530690816171357289175
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log

  UVM_FATAL @ 194178.7 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000800
  UVM_INFO @ 194178.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test flash_ctrl_integrity has 5 failures.

0.flash_ctrl_integrity.79954844733782541199931023009951477071572387279110153369772374251128674316101
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log

  UVM_FATAL @ 1116024.4 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000026f8
  UVM_INFO @ 1116024.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_integrity.50337182589082485056785161602502856445197013341859829214850601496452248438332
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log

  UVM_FATAL @ 2065777.6 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00003890
  UVM_INFO @ 2065777.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_prog_reset_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 23 failures:

Test flash_ctrl_prog_reset has 23 failures.

0.flash_ctrl_prog_reset.98122867468395338766470468401207740074420007674945906482883552078382930320504
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_prog_reset/latest/run.log

  UVM_ERROR @ 12132.3 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 12132.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_prog_reset.54965848304975711071335615325320046276053588716280110420448854783170801763996
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_prog_reset/latest/run.log

  UVM_ERROR @ 22931.9 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 22931.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 21 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 18 failures:

Test flash_ctrl_intr_wr has 9 failures.

0.flash_ctrl_intr_wr.94027719808465561889328670668071302734703410100655974564686087252358686416846
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr/latest/run.log

  UVM_ERROR @ 47505.6 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 47505.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_intr_wr.108543637784594611972772371002693163305591374495124759602746972511786142999031
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr/latest/run.log

  UVM_ERROR @ 19436.0 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 19436.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

Test flash_ctrl_intr_wr_slow_flash has 9 failures.

0.flash_ctrl_intr_wr_slow_flash.2836804763121269917869284111315727973445903996147033137606998642086306660425
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr_slow_flash/latest/run.log

  UVM_ERROR @ 26103.8 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 26103.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_intr_wr_slow_flash.70403405953215092157573438773964210204448388129897926172796494461334160738117
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr_slow_flash/latest/run.log

  UVM_ERROR @ 42685.3 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 42685.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_rw_evict_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 18 failures:

Test flash_ctrl_rw_evict has 7 failures.

9.flash_ctrl_rw_evict.26913925016000809729777601181047510733719754786474913887940571557807785094246
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 64911.2 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 64911.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.flash_ctrl_rw_evict.26545004859527358128610826203719171285198468805565861687227134580044473781982
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 30512.0 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 30512.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test flash_ctrl_rw_evict_all_en has 11 failures.

12.flash_ctrl_rw_evict_all_en.104926066853229694559117518482198249496440135370674950970381399108650025986653
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 9283.9 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 9283.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

13.flash_ctrl_rw_evict_all_en.81747368949842092002288225409183991763156563939593097505252125324416856886148
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 9773.3 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 9773.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_disable_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 11 failures:

Test flash_ctrl_disable has 11 failures.

2.flash_ctrl_disable.7759488589640129093571325674952286905722036030324821122080648543225845465552
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 31952.2 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 31952.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.flash_ctrl_disable.104601808739846928150002832336692450154753334591043390237009087515857903908326
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 9941.5 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 9941.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_prog_reset_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 6 failures:
- Test flash_ctrl_prog_reset has 6 failures.
  - 4.flash_ctrl_prog_reset.23263261188921399436336760706699550432695404546567415142925626471855922765871
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_prog_reset/latest/run.log
```
  UVM_ERROR @ 4580.0 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 4580.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 7.flash_ctrl_prog_reset.40038811231756108037313029030003198570221188924297048732751035174042311105047
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_prog_reset/latest/run.log
```
  UVM_ERROR @ 4957.4 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 4957.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 4 more failures.
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_serr_counter_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 5 failures:
- Test flash_ctrl_serr_counter has 5 failures.
  - 0.flash_ctrl_serr_counter.53154437330807256521290243655242842918375772824900384852405290821440110264070
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_serr_counter/latest/run.log
```
  UVM_FATAL @ 300549.1 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_counter_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00002658
  UVM_INFO @ 300549.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.flash_ctrl_serr_counter.27223040295020783483396250750745122529878888755676282150826919767664669486229
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_serr_counter/latest/run.log
```
  UVM_FATAL @ 111642.0 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_counter_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000cd928
  UVM_INFO @ 111642.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_filesystem_support_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 5 failures:

Test flash_ctrl_fs_sup has 5 failures.

0.flash_ctrl_fs_sup.19065523829164429593779299741559402498059059087936282006756793012430054035791
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_fs_sup/latest/run.log

  UVM_FATAL @ 16894.5 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_filesystem_support_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000e90
  UVM_INFO @ 16894.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_fs_sup.83671519895900779117903333245277810248798149743253896436638812088062865137775
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_fs_sup/latest/run.log

  UVM_FATAL @ 71765.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_filesystem_support_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001558
  UVM_INFO @ 71765.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_disable_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 5 failures:
- Test flash_ctrl_disable has 5 failures.
  - 12.flash_ctrl_disable.60635219603076705560534420011025539625201793282526990121065695814050182520386
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_disable/latest/run.log
```
  UVM_ERROR @ 75798.5 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 75798.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.flash_ctrl_disable.50733763334402769451360544637814036849549673774417689187315225597647454312808
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_disable/latest/run.log
```
  UVM_ERROR @ 4554.8 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 4554.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_serr_address_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 4 failures:
- Test flash_ctrl_serr_address has 4 failures.
  - 0.flash_ctrl_serr_address.22479134266552262328289694963698584391553086386766949145515059942741123306849
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_serr_address/latest/run.log
```
  UVM_FATAL @ 408263.9 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_address_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x0002d2b0
  UVM_INFO @ 408263.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.flash_ctrl_serr_address.104614269335948407892797689141019567302217152636141819685936474598956746096247
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_serr_address/latest/run.log
```
  UVM_FATAL @ 1171387.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_address_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00002470
  UVM_INFO @ 1171387.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_oversize_error_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 3 failures:
- Test flash_ctrl_oversize_error has 3 failures.
  - 0.flash_ctrl_oversize_error.64653083917019515823512058920367667181817100511811147474965845021509166893224
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_oversize_error/latest/run.log
```
  UVM_ERROR @ 21607.4 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_oversize_error_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 21607.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.flash_ctrl_oversize_error.95714365709608762501318366155979401952656887895730556686890601449175600574058
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_oversize_error/latest/run.log
```
  UVM_ERROR @ 4632.9 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_oversize_error_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 4632.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_common_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 3 failures:

Test flash_ctrl_sec_cm has 3 failures.

0.flash_ctrl_sec_cm.46842318966166210823880924017928743337659782537106492495620705834117965322235
Line 298, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_sec_cm/latest/run.log

  UVM_ERROR @ 11736.0 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 11736.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_sec_cm.26961658912191191169152678262324003772080228184541859810470917116353985758468
Line 299, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_sec_cm/latest/run.log

  UVM_ERROR @ 4629.1 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 4629.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_derr_detect_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 2 failures:

Test flash_ctrl_derr_detect has 2 failures.

0.flash_ctrl_derr_detect.12035681399981266553956166857055434826235108502751893455268698151286168828719
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log

  UVM_ERROR @ 19152.0 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_derr_detect_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 19152.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_derr_detect.58326391463876617479910153415394754979271915132339777136955525236645293111359
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log

  UVM_ERROR @ 4845.3 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_derr_detect_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 4845.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_access_after_disable_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 2 failures:
- Test flash_ctrl_access_after_disable has 2 failures.
  - 0.flash_ctrl_access_after_disable.48194530819668965065532473545767845414509506054409425224157513290259096963552
    Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_access_after_disable/latest/run.log
```
  UVM_ERROR @ 19539.4 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_access_after_disable_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 19539.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.flash_ctrl_access_after_disable.24785169824248028649043131139155285587094807314384554503521538099822370146149
    Line 295, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_access_after_disable/latest/run.log
```
  UVM_ERROR @ 19836.4 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_access_after_disable_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 19836.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_oversize_error_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 2 failures:

Test flash_ctrl_oversize_error has 2 failures.

1.flash_ctrl_oversize_error.38574792615896454149769125987079651392522605640163039653978492621484594948771
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_oversize_error/latest/run.log

  UVM_ERROR @ 11877.6 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_oversize_error_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 11877.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_oversize_error.2532017442595871020019880588961538730745535481100859201639953590517703553448
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_oversize_error/latest/run.log

  UVM_ERROR @ 134561.1 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_oversize_error_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 134561.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 2 failures:
- Test flash_ctrl_rw_evict has 2 failures.
  - 1.flash_ctrl_rw_evict.21926584251600801503861668417107187563961614548994748529434910420995562557492
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest/run.log
```
  UVM_FATAL @ 9840.0 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00002278
  UVM_INFO @ 9840.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.flash_ctrl_rw_evict.26618904621105522413560682653385326862797233807410815089876476042526304014889
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict/latest/run.log
```
  UVM_FATAL @ 10070.6 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001a28
  UVM_INFO @ 10070.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_intr_wr_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 2 failures:
- Test flash_ctrl_intr_wr has 1 failures.
  - 3.flash_ctrl_intr_wr.9610432636980888790068917724629944569889029246741590532705693529215516488000
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr/latest/run.log
```
  UVM_FATAL @ 144876.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001360
  UVM_INFO @ 144876.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_intr_wr_slow_flash has 1 failures.
  - 5.flash_ctrl_intr_wr_slow_flash.52980836278630265685008817653417210549533994085659049091626416434582801844435
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr_slow_flash/latest/run.log
```
  UVM_FATAL @ 1675079.9 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000ab8
  UVM_INFO @ 1675079.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_write_word_sweep_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 1 failures:
- Test flash_ctrl_write_word_sweep has 1 failures.
  - 0.flash_ctrl_write_word_sweep.31595728928888919549000466076515170140769545339401685413086523025460575149885
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_write_word_sweep/latest/run.log
```
  UVM_ERROR @ 4746.6 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_write_word_sweep_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 4746.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_access_after_disable_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 1 failures:
- Test flash_ctrl_access_after_disable has 1 failures.
  - 1.flash_ctrl_access_after_disable.68106871435106650628144151461839334015399242943132254120870314905472494772256
    Line 295, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_access_after_disable/latest/run.log
```
  UVM_ERROR @ 20939.8 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_access_after_disable_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 20939.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_derr_detect_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 2.flash_ctrl_derr_detect.90151869969264075339890275615067759637321842710207886524168228505435952741861
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log
```
  UVM_FATAL @ 21330.9 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_derr_detect_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000014e0
  UVM_INFO @ 21330.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_common_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_sec_cm has 1 failures.
  - 2.flash_ctrl_sec_cm.68596851250873958716357924267102037234154574855742880328983887505285481537923
    Line 302, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_sec_cm/latest/run.log
```
  UVM_FATAL @ 18969.9 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001f88
  UVM_INFO @ 18969.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_common_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 1 failures:
- Test flash_ctrl_sec_cm has 1 failures.
  - 3.flash_ctrl_sec_cm.115153152904808124042670048079603398829019969354248166277706276697310076159394
    Line 298, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @ 3564.2 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 3564.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_derr_detect_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 1 failures:
- Test flash_ctrl_derr_detect has 1 failures.
  - 4.flash_ctrl_derr_detect.59551744332523914712777045932760674967209717800662625370603180661541180072965
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 9774.9 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_derr_detect_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 9774.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_rw has 1 failures.
  - 14.flash_ctrl_rw.95400786415972124302583347343591821321596414977498035805165595630413724479013
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_rw/latest/run.log
```
  UVM_ERROR @ 772917.3 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 772917.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```