FLASH_CTRL Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: ecd9f08747

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke flash_ctrl_smoke 3.348m 686.644us 50 50 100.00
V1 smoke_hw flash_ctrl_smoke_hw 26.040s 22.682us 5 5 100.00
V1 csr_hw_reset flash_ctrl_csr_hw_reset 46.770s 85.961us 5 5 100.00
V1 csr_rw flash_ctrl_csr_rw 17.820s 97.623us 20 20 100.00
V1 csr_bit_bash flash_ctrl_csr_bit_bash 1.206m 2.841ms 5 5 100.00
V1 csr_aliasing flash_ctrl_csr_aliasing 1.074m 5.087ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset flash_ctrl_csr_mem_rw_with_rand_reset 19.900s 181.020us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr flash_ctrl_csr_rw 17.820s 97.623us 20 20 100.00
flash_ctrl_csr_aliasing 1.074m 5.087ms 5 5 100.00
V1 mem_walk flash_ctrl_mem_walk 13.610s 19.038us 5 5 100.00
V1 mem_partial_access flash_ctrl_mem_partial_access 13.960s 30.552us 5 5 100.00
V1 TOTAL 120 120 100.00
V2 sw_op flash_ctrl_sw_op 26.800s 25.428us 5 5 100.00
V2 host_read_direct flash_ctrl_host_dir_rd 2.061m 248.434us 5 5 100.00
V2 rma_hw_if flash_ctrl_hw_rma 36.065m 334.104ms 3 3 100.00
flash_ctrl_hw_rma_reset 16.555m 170.172ms 20 20 100.00
flash_ctrl_lcmgr_intg 13.830s 15.515us 20 20 100.00
V2 host_controller_arb flash_ctrl_host_ctrl_arb 48.173m 303.313ms 5 5 100.00
V2 erase_suspend flash_ctrl_erase_suspend 8.960m 8.185ms 5 5 100.00
V2 program_reset flash_ctrl_prog_reset 13.710s 9.042us 2 30 6.67
V2 full_memory_access flash_ctrl_full_mem_access 51.916m 783.522ms 5 5 100.00
V2 rd_buff_eviction flash_ctrl_rd_buff_evict 4.141m 2.091ms 5 5 100.00
V2 rd_buff_eviction_w_ecc flash_ctrl_rw_evict 32.640s 33.897us 6 40 15.00
flash_ctrl_rw_evict_all_en 32.360s 44.153us 2 40 5.00
flash_ctrl_re_evict 37.820s 473.477us 20 20 100.00
V2 host_arb flash_ctrl_phy_arb 9.062m 5.766ms 20 20 100.00
V2 host_interleave flash_ctrl_phy_arb 9.062m 5.766ms 20 20 100.00
V2 memory_protection flash_ctrl_mp_regions 20.714m 31.490ms 20 20 100.00
V2 fetch_code flash_ctrl_fetch_code 29.180s 1.115ms 10 10 100.00
V2 all_partitions flash_ctrl_rand_ops 21.730m 164.130us 20 20 100.00
V2 error_mp flash_ctrl_error_mp 46.061m 14.892ms 10 10 100.00
V2 error_prog_win flash_ctrl_error_prog_win 17.270m 1.585ms 10 10 100.00
V2 error_prog_type flash_ctrl_error_prog_type 46.148m 1.266ms 5 5 100.00
V2 error_read_seed flash_ctrl_hw_read_seed_err 14.100s 14.848us 20 20 100.00
V2 read_write_overflow flash_ctrl_oversize_error 41.050s 313.587us 0 5 0.00
V2 flash_ctrl_disable flash_ctrl_disable 22.660s 31.647us 35 50 70.00
V2 flash_ctrl_connect flash_ctrl_connect 16.160s 15.925us 80 80 100.00
V2 stress_all flash_ctrl_stress_all 25.144m 969.621us 5 5 100.00
V2 secret_partition flash_ctrl_hw_sec_otp 4.042m 8.366ms 50 50 100.00
flash_ctrl_otp_reset 2.290m 145.614us 80 80 100.00
V2 isolation_partition flash_ctrl_hw_rma 36.065m 334.104ms 3 3 100.00
V2 interrupts flash_ctrl_intr_rd 3.312m 2.051ms 40 40 100.00
flash_ctrl_intr_wr 23.280s 459.628us 0 10 0.00
flash_ctrl_intr_rd_slow_flash 5.219m 42.062ms 40 40 100.00
flash_ctrl_intr_wr_slow_flash 24.510s 1.695ms 0 10 0.00
V2 invalid_op flash_ctrl_invalid_op 1.502m 1.009ms 20 20 100.00
V2 mid_op_rst flash_ctrl_mid_op_rst 1.205m 3.954ms 5 5 100.00
V2 double_bit_err flash_ctrl_read_word_sweep_derr 22.810s 19.766us 5 5 100.00
flash_ctrl_ro_derr 2.747m 3.187ms 10 10 100.00
flash_ctrl_rw_derr 8.780m 4.996ms 0 10 0.00
flash_ctrl_derr_detect 1.067m 168.964us 0 5 0.00
flash_ctrl_integrity 2.163m 2.639ms 0 5 0.00
V2 single_bit_err flash_ctrl_read_word_sweep_serr 22.900s 44.221us 5 5 100.00
flash_ctrl_ro_serr 2.730m 946.290us 10 10 100.00
flash_ctrl_rw_serr 3.292m 7.546ms 0 10 0.00
V2 singlebit_err_counter flash_ctrl_serr_counter 1.115m 2.533ms 1 5 20.00
V2 singlebit_err_address flash_ctrl_serr_address 1.516m 850.421us 0 5 0.00
V2 scramble flash_ctrl_wo 4.077m 6.194ms 20 20 100.00
flash_ctrl_write_word_sweep 13.400s 18.916us 0 1 0.00
flash_ctrl_read_word_sweep 13.910s 25.903us 1 1 100.00
flash_ctrl_ro 2.200m 1.780ms 19 20 95.00
flash_ctrl_rw 10.935m 4.775ms 20 20 100.00
V2 filesystem_support flash_ctrl_fs_sup 37.780s 377.726us 3 5 60.00
V2 rma_write_process_error flash_ctrl_rma_err 18.335m 281.126ms 3 3 100.00
flash_ctrl_hw_prog_rma_wipe_err 5.195m 10.012ms 20 20 100.00
V2 alert_test flash_ctrl_alert_test 14.610s 70.340us 50 50 100.00
V2 intr_test flash_ctrl_intr_test 14.300s 17.708us 50 50 100.00
V2 tl_d_oob_addr_access flash_ctrl_tl_errors 20.670s 247.937us 20 20 100.00
V2 tl_d_illegal_access flash_ctrl_tl_errors 20.670s 247.937us 20 20 100.00
V2 tl_d_outstanding_access flash_ctrl_csr_hw_reset 46.770s 85.961us 5 5 100.00
flash_ctrl_csr_rw 17.820s 97.623us 20 20 100.00
flash_ctrl_csr_aliasing 1.074m 5.087ms 5 5 100.00
flash_ctrl_same_csr_outstanding 20.820s 208.847us 20 20 100.00
V2 tl_d_partial_access flash_ctrl_csr_hw_reset 46.770s 85.961us 5 5 100.00
flash_ctrl_csr_rw 17.820s 97.623us 20 20 100.00
flash_ctrl_csr_aliasing 1.074m 5.087ms 5 5 100.00
flash_ctrl_same_csr_outstanding 20.820s 208.847us 20 20 100.00
V2 TOTAL 830 1013 81.93
V2S shadow_reg_update_error flash_ctrl_shadow_reg_errors 16.050s 23.613us 20 20 100.00
V2S shadow_reg_read_clear_staged_value flash_ctrl_shadow_reg_errors 16.050s 23.613us 20 20 100.00
V2S shadow_reg_storage_error flash_ctrl_shadow_reg_errors 16.050s 23.613us 20 20 100.00
V2S shadowed_reset_glitch flash_ctrl_shadow_reg_errors 16.050s 23.613us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw flash_ctrl_shadow_reg_errors_with_csr_rw 16.060s 105.994us 20 20 100.00
V2S tl_intg_err flash_ctrl_sec_cm 15.810s 5.902us 0 5 0.00
flash_ctrl_tl_intg_err 15.347m 4.644ms 20 20 100.00
V2S sec_cm_reg_bus_integrity flash_ctrl_tl_intg_err 15.347m 4.644ms 20 20 100.00
V2S sec_cm_host_bus_integrity flash_ctrl_tl_intg_err 15.347m 4.644ms 20 20 100.00
V2S sec_cm_mem_bus_integrity flash_ctrl_rd_intg 32.410s 321.457us 3 3 100.00
flash_ctrl_wr_intg 14.940s 173.923us 3 3 100.00
V2S sec_cm_scramble_key_sideload flash_ctrl_smoke 3.348m 686.644us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi flash_ctrl_otp_reset 2.290m 145.614us 80 80 100.00
flash_ctrl_disable 22.660s 31.647us 35 50 70.00
flash_ctrl_sec_info_access 1.399m 24.758ms 50 50 100.00
flash_ctrl_connect 16.160s 15.925us 80 80 100.00
V2S sec_cm_ctrl_config_regwen flash_ctrl_config_regwen 14.160s 22.341us 5 5 100.00
V2S sec_cm_data_regions_config_regwen flash_ctrl_csr_rw 17.820s 97.623us 20 20 100.00
V2S sec_cm_data_regions_config_shadow flash_ctrl_shadow_reg_errors 16.050s 23.613us 20 20 100.00
V2S sec_cm_info_regions_config_regwen flash_ctrl_csr_rw 17.820s 97.623us 20 20 100.00
V2S sec_cm_info_regions_config_shadow flash_ctrl_shadow_reg_errors 16.050s 23.613us 20 20 100.00
V2S sec_cm_bank_config_regwen flash_ctrl_csr_rw 17.820s 97.623us 20 20 100.00
V2S sec_cm_bank_config_shadow flash_ctrl_shadow_reg_errors 16.050s 23.613us 20 20 100.00
V2S sec_cm_mem_ctrl_global_esc flash_ctrl_disable 22.660s 31.647us 35 50 70.00
V2S sec_cm_mem_ctrl_local_esc flash_ctrl_rd_intg 32.410s 321.457us 3 3 100.00
flash_ctrl_access_after_disable 13.780s 15.300us 1 3 33.33
V2S sec_cm_mem_disable_config_mubi flash_ctrl_disable 22.660s 31.647us 35 50 70.00
V2S sec_cm_exec_config_redun flash_ctrl_fetch_code 29.180s 1.115ms 10 10 100.00
V2S sec_cm_mem_scramble flash_ctrl_rw 10.935m 4.775ms 20 20 100.00
V2S sec_cm_mem_integrity flash_ctrl_rw_serr 3.292m 7.546ms 0 10 0.00
flash_ctrl_rw_derr 8.780m 4.996ms 0 10 0.00
flash_ctrl_integrity 2.163m 2.639ms 0 5 0.00
V2S sec_cm_rma_entry_mem_sec_wipe flash_ctrl_hw_rma 36.065m 334.104ms 3 3 100.00
V2S sec_cm_ctrl_fsm_sparse flash_ctrl_sec_cm 15.810s 5.902us 0 5 0.00
V2S sec_cm_phy_fsm_sparse flash_ctrl_sec_cm 15.810s 5.902us 0 5 0.00
V2S sec_cm_phy_prog_fsm_sparse flash_ctrl_sec_cm 15.810s 5.902us 0 5 0.00
V2S sec_cm_ctr_redun flash_ctrl_sec_cm 15.810s 5.902us 0 5 0.00
V2S sec_cm_phy_arbiter_ctrl_redun flash_ctrl_phy_arb_redun 20.820s 626.050us 5 5 100.00
V2S sec_cm_phy_host_grant_ctrl_consistency flash_ctrl_phy_host_grant_err 14.650s 46.027us 5 5 100.00
V2S sec_cm_phy_ack_ctrl_consistency flash_ctrl_phy_ack_consistency 14.050s 27.641us 5 5 100.00
V2S sec_cm_fifo_ctr_redun flash_ctrl_sec_cm 15.810s 5.902us 0 5 0.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse flash_ctrl_sec_cm 15.810s 5.902us 0 5 0.00
V2S sec_cm_prog_tl_lc_gate_fsm_sparse flash_ctrl_sec_cm 15.810s 5.902us 0 5 0.00
V2S TOTAL 137 144 95.14
V3 asymmetric_read_path flash_ctrl_rd_ooo 43.620s 67.436us 1 1 100.00
V3 stress_all_with_rand_reset flash_ctrl_stress_all_with_rand_reset 0 0 --
V3 TOTAL 1 1 100.00
TOTAL 1088 1278 85.13

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 55 55 39 70.91
V2S 12 12 10 83.33
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.94 95.77 93.29 94.81 90.48 97.86 94.71 97.69

Failure Buckets

Past Results