FLASH_CTRL Simulation Results

Thursday May 02 2024 19:03:09 UTC

GitHub Revision: `ecd9f08747`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 19770536698299155636913061839112149222426010608929753156399703507865583879800

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.348m	686.644us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.040s	22.682us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.770s	85.961us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.820s	97.623us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.206m	2.841ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.074m	5.087ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.900s	181.020us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.820s	97.623us	20	20	100.00
		flash_ctrl_csr_aliasing	1.074m	5.087ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.610s	19.038us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	13.960s	30.552us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.800s	25.428us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.061m	248.434us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	36.065m	334.104ms	3	3	100.00
		flash_ctrl_hw_rma_reset	16.555m	170.172ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.830s	15.515us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	48.173m	303.313ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	8.960m	8.185ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	13.710s	9.042us	2	30	6.67
V2	full_memory_access	flash_ctrl_full_mem_access	51.916m	783.522ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	4.141m	2.091ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	32.640s	33.897us	6	40	15.00
		flash_ctrl_rw_evict_all_en	32.360s	44.153us	2	40	5.00
		flash_ctrl_re_evict	37.820s	473.477us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.062m	5.766ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.062m	5.766ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	20.714m	31.490ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	29.180s	1.115ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	21.730m	164.130us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	46.061m	14.892ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.270m	1.585ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	46.148m	1.266ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.100s	14.848us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	41.050s	313.587us	0	5	0.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.660s	31.647us	35	50	70.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.160s	15.925us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	25.144m	969.621us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.042m	8.366ms	50	50	100.00
		flash_ctrl_otp_reset	2.290m	145.614us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	36.065m	334.104ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.312m	2.051ms	40	40	100.00
		flash_ctrl_intr_wr	23.280s	459.628us	0	10	0.00
		flash_ctrl_intr_rd_slow_flash	5.219m	42.062ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	24.510s	1.695ms	0	10	0.00
V2	invalid_op	flash_ctrl_invalid_op	1.502m	1.009ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.205m	3.954ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.810s	19.766us	5	5	100.00
		flash_ctrl_ro_derr	2.747m	3.187ms	10	10	100.00
		flash_ctrl_rw_derr	8.780m	4.996ms	0	10	0.00
		flash_ctrl_derr_detect	1.067m	168.964us	0	5	0.00
		flash_ctrl_integrity	2.163m	2.639ms	0	5	0.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.900s	44.221us	5	5	100.00
		flash_ctrl_ro_serr	2.730m	946.290us	10	10	100.00
		flash_ctrl_rw_serr	3.292m	7.546ms	0	10	0.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.115m	2.533ms	1	5	20.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.516m	850.421us	0	5	0.00
V2	scramble	flash_ctrl_wo	4.077m	6.194ms	20	20	100.00
		flash_ctrl_write_word_sweep	13.400s	18.916us	0	1	0.00
		flash_ctrl_read_word_sweep	13.910s	25.903us	1	1	100.00
		flash_ctrl_ro	2.200m	1.780ms	19	20	95.00
		flash_ctrl_rw	10.935m	4.775ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	37.780s	377.726us	3	5	60.00
V2	rma_write_process_error	flash_ctrl_rma_err	18.335m	281.126ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.195m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.610s	70.340us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.300s	17.708us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.670s	247.937us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.670s	247.937us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.770s	85.961us	5	5	100.00
		flash_ctrl_csr_rw	17.820s	97.623us	20	20	100.00
		flash_ctrl_csr_aliasing	1.074m	5.087ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	20.820s	208.847us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.770s	85.961us	5	5	100.00
		flash_ctrl_csr_rw	17.820s	97.623us	20	20	100.00
		flash_ctrl_csr_aliasing	1.074m	5.087ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	20.820s	208.847us	20	20	100.00
V2		TOTAL			830	1013	81.93
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.050s	23.613us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.050s	23.613us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.050s	23.613us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.050s	23.613us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.060s	105.994us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	15.810s	5.902us	0	5	0.00
		flash_ctrl_tl_intg_err	15.347m	4.644ms	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.347m	4.644ms	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.347m	4.644ms	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.410s	321.457us	3	3	100.00
		flash_ctrl_wr_intg	14.940s	173.923us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.348m	686.644us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.290m	145.614us	80	80	100.00
		flash_ctrl_disable	22.660s	31.647us	35	50	70.00
		flash_ctrl_sec_info_access	1.399m	24.758ms	50	50	100.00
		flash_ctrl_connect	16.160s	15.925us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.160s	22.341us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.820s	97.623us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.050s	23.613us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.820s	97.623us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.050s	23.613us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.820s	97.623us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.050s	23.613us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.660s	31.647us	35	50	70.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.410s	321.457us	3	3	100.00
		flash_ctrl_access_after_disable	13.780s	15.300us	1	3	33.33
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.660s	31.647us	35	50	70.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	29.180s	1.115ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	10.935m	4.775ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	3.292m	7.546ms	0	10	0.00
		flash_ctrl_rw_derr	8.780m	4.996ms	0	10	0.00
		flash_ctrl_integrity	2.163m	2.639ms	0	5	0.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	36.065m	334.104ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	15.810s	5.902us	0	5	0.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	15.810s	5.902us	0	5	0.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	15.810s	5.902us	0	5	0.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	15.810s	5.902us	0	5	0.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	20.820s	626.050us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.650s	46.027us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.050s	27.641us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	15.810s	5.902us	0	5	0.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	15.810s	5.902us	0	5	0.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	15.810s	5.902us	0	5	0.00
V2S		TOTAL			137	144	95.14
V3	asymmetric_read_path	flash_ctrl_rd_ooo	43.620s	67.436us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1088	1278	85.13

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	39	70.91
V2S	12	12	10	83.33
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.94	95.77	93.29	94.81	90.48	97.86	94.71	97.69

Failure Buckets

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 46 failures:

Test flash_ctrl_rw_evict_all_en has 29 failures.

0.flash_ctrl_rw_evict_all_en.6942965634571643715914563026360002770799136648134366189361486692967818376436
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 10019.2 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 10019.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_rw_evict_all_en.87183633573687964956132883665613717532886397435088294615380465759720440583652
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 9498.5 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 9498.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 27 more failures.

Test flash_ctrl_rw_evict has 17 failures.

1.flash_ctrl_rw_evict.29630714284409850620444804200503488338850723945329472464367394454245096420346
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 72021.7 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 72021.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.flash_ctrl_rw_evict.60567668359902593573460676716955142762568391075127248850971092722325615053701
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 8640.1 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 8640.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 15 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 25 failures:

Test flash_ctrl_rw_serr has 10 failures.

0.flash_ctrl_rw_serr.105763635829508750326603447342600200815894683568435944283900315633895862698979
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest/run.log

  UVM_FATAL @ 105422.4 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001628
  UVM_INFO @ 105422.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_rw_serr.50620121175741701296032739649733249611420117883879142550144459335761295948467
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log

  UVM_FATAL @ 7256550.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00004cc0
  UVM_INFO @ 7256550.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test flash_ctrl_rw_derr has 10 failures.

0.flash_ctrl_rw_derr.3104264719141297835521303533361600541426486190955323968392785135849940120018
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest/run.log

  UVM_FATAL @ 2106649.8 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00002be8
  UVM_INFO @ 2106649.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_rw_derr.1957708022171785098331140312076290279158555427923719308303191344712582655812
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log

  UVM_FATAL @ 2165282.5 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00002db0
  UVM_INFO @ 2165282.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test flash_ctrl_integrity has 5 failures.

0.flash_ctrl_integrity.84437577726346083389887214050279531650976736940690227277843614671906380531610
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log

  UVM_FATAL @ 1063048.0 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000017a0
  UVM_INFO @ 1063048.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_integrity.24929005336203663691177909647140110525462599279284812250239615217009692703667
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log

  UVM_FATAL @ 2638804.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00003d98
  UVM_INFO @ 2638804.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_rw_evict_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 23 failures:

Test flash_ctrl_rw_evict has 15 failures.

0.flash_ctrl_rw_evict.107988299528214750373737260975751956784613448527740166088844926430183796139893
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 8397.0 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 8397.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_rw_evict.13835886942374829703760016026301931123472242412637328508631579411239854260723
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 16710.6 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 16710.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 13 more failures.

Test flash_ctrl_rw_evict_all_en has 8 failures.

3.flash_ctrl_rw_evict_all_en.59300356584675544342401216255902711184000404561505168184486999312478058265583
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 40443.5 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 40443.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.flash_ctrl_rw_evict_all_en.54713924285363861687115492822038124934035563589053563390722143510630305389248
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 154407.2 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 154407.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_prog_reset_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 17 failures:

Test flash_ctrl_prog_reset has 17 failures.

1.flash_ctrl_prog_reset.89388825572618319133191035908400560513689159116824223811290067351149339496048
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_prog_reset/latest/run.log

  UVM_ERROR @ 5097.1 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 5097.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_prog_reset.37717289268895853786900143115886600626040564964255994736841004149323208886816
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_prog_reset/latest/run.log

  UVM_ERROR @ 18423.5 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 18423.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 15 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 16 failures:

Test flash_ctrl_intr_wr has 8 failures.

0.flash_ctrl_intr_wr.47526425220815918406964701243326244069623392326353119495842661943874578200471
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr/latest/run.log

  UVM_ERROR @ 89640.7 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 89640.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_intr_wr.73453463995625863286681026852029336863621079117725572961628072473126795376251
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr/latest/run.log

  UVM_ERROR @ 9459.9 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 9459.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test flash_ctrl_intr_wr_slow_flash has 8 failures.

1.flash_ctrl_intr_wr_slow_flash.37221542850942298128902175187383542504505534878561305580570873155278650505849
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr_slow_flash/latest/run.log

  UVM_ERROR @ 81478.8 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 81478.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_intr_wr_slow_flash.53922728750382982311572427460302407762144717297107382584476249861130872866946
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr_slow_flash/latest/run.log

  UVM_ERROR @ 1155509.8 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 1155509.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_prog_reset_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 11 failures:
- Test flash_ctrl_prog_reset has 11 failures.
  - 0.flash_ctrl_prog_reset.92822878687318186139249750249506618437794290050756169877694352632260308686168
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_prog_reset/latest/run.log
```
  UVM_ERROR @ 81230.5 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 81230.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.flash_ctrl_prog_reset.94404072543118616014634194810828409384654452097884417048079233673678114011121
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_prog_reset/latest/run.log
```
  UVM_ERROR @ 4867.3 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 4867.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_disable_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 10 failures:

Test flash_ctrl_disable has 10 failures.

1.flash_ctrl_disable.97608124445051067958390587869646855511293241900724979190720838598767510216970
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 18182.2 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 18182.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_disable.21894373096758856355073335141883234566800550763133445806655903396964779721828
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 23621.3 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 23621.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_serr_address_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 5 failures:
- Test flash_ctrl_serr_address has 5 failures.
  - 0.flash_ctrl_serr_address.41580299980681007384627050169182768819548759417642753419526209048431161243127
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_serr_address/latest/run.log
```
  UVM_FATAL @ 927047.1 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_address_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00002d58
  UVM_INFO @ 927047.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.flash_ctrl_serr_address.13730775738385396910742910756100316309804186313221499544222347874014603667847
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_serr_address/latest/run.log
```
  UVM_FATAL @ 850421.4 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_address_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00004718
  UVM_INFO @ 850421.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_serr_counter_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 4 failures:
- Test flash_ctrl_serr_counter has 4 failures.
  - 0.flash_ctrl_serr_counter.9576077391215458628298489328872678889846798081138470694945734101830682701933
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_serr_counter/latest/run.log
```
  UVM_FATAL @ 365546.5 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_counter_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00004120
  UVM_INFO @ 365546.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.flash_ctrl_serr_counter.6342631170781132010794238026159237935505166197675654519383180703078019659782
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_serr_counter/latest/run.log
```
  UVM_FATAL @ 364145.5 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_counter_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00003760
  UVM_INFO @ 364145.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_intr_wr_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 4 failures:

Test flash_ctrl_intr_wr_slow_flash has 2 failures.

0.flash_ctrl_intr_wr_slow_flash.52697370266414716798071049389307107473655557549765655923818116355586976887887
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr_slow_flash/latest/run.log

  UVM_FATAL @ 408448.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000b68
  UVM_INFO @ 408448.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_intr_wr_slow_flash.109744673680963226349132024782456438879646873557397722902685605231668879089007
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr_slow_flash/latest/run.log

  UVM_FATAL @ 5265923.4 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001658
  UVM_INFO @ 5265923.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_intr_wr has 2 failures.

1.flash_ctrl_intr_wr.61600827003194321799672985272823433965343694401737473948949037328306166308915
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr/latest/run.log

  UVM_FATAL @ 37251.8 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000c38
  UVM_INFO @ 37251.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_intr_wr.1060470899157784094366173689672801005236976274922372550438589750184127751137
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr/latest/run.log

  UVM_FATAL @ 459628.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00004468
  UVM_INFO @ 459628.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_disable_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 4 failures:
- Test flash_ctrl_disable has 4 failures.
  - 4.flash_ctrl_disable.27668209268073641831555900346273945229291397246774993901561759625808254632442
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_disable/latest/run.log
```
  UVM_ERROR @ 7752.2 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 7752.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 14.flash_ctrl_disable.88009683989437418303812775537720291079408076985212135413300705675722741943512
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_disable/latest/run.log
```
  UVM_ERROR @ 22257.2 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 22257.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_common_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 3 failures:

Test flash_ctrl_sec_cm has 3 failures.

0.flash_ctrl_sec_cm.83025791077360912198396285583125172453269132208403792768210845692928030357428
Line 288, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_sec_cm/latest/run.log

  UVM_ERROR @ 10154.2 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 10154.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_sec_cm.74691256257946037698285121894621520873562687326660574763891192472842010815126
Line 288, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_sec_cm/latest/run.log

  UVM_ERROR @ 5902.2 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 5902.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_derr_detect_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 3 failures:

Test flash_ctrl_derr_detect has 3 failures.

2.flash_ctrl_derr_detect.6976131934852613190652369693344983373744180227637666833364643553151644260022
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest/run.log

  UVM_ERROR @ 265985.4 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_derr_detect_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 265985.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_derr_detect.65443800679342099202016856189507409412788254214740938930110828952319953979337
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log

  UVM_ERROR @ 5729.2 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_derr_detect_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 5729.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_oversize_error_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 3 failures:

Test flash_ctrl_oversize_error has 3 failures.

2.flash_ctrl_oversize_error.102364080278742136068760412713623778371142966243539791279938285586115958944644
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_oversize_error/latest/run.log

  UVM_ERROR @ 100605.9 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_oversize_error_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 100605.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_oversize_error.70613203361625689673756630878467837728174807584539112661745279785818784112228
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_oversize_error/latest/run.log

  UVM_ERROR @ 17684.6 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_oversize_error_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 17684.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 3 failures:

Test flash_ctrl_rw_evict_all_en has 1 failures.

17.flash_ctrl_rw_evict_all_en.103924707311714873833027941091375624719259349879337425637057753667966513399152
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 7845.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001178
  UVM_INFO @ 7845.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_evict has 2 failures.

27.flash_ctrl_rw_evict.46523847565954271593199614988494940650024859139211848481983639423314753042004
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 54168.1 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001680
  UVM_INFO @ 54168.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

32.flash_ctrl_rw_evict.77210157429943328588147419138400965482351699838584865049946383553845938297834
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 21904.5 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00081028
  UVM_INFO @ 21904.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_derr_detect_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 2 failures:
- Test flash_ctrl_derr_detect has 2 failures.
  - 0.flash_ctrl_derr_detect.67758796108328294651806038218104467052347258020746712736360849506371004407348
    Line 303, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 168963.9 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_derr_detect_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 168963.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.flash_ctrl_derr_detect.59639373206099170107691406075942316171221540521082748401741584017697849518053
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 45501.8 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_derr_detect_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 45501.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_filesystem_support_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 2 failures:

Test flash_ctrl_fs_sup has 2 failures.

0.flash_ctrl_fs_sup.100501084825720131186909835349501507742716484967100210001096149344600619095116
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_fs_sup/latest/run.log

  UVM_FATAL @ 338488.9 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_filesystem_support_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001078
  UVM_INFO @ 338488.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_fs_sup.73724891677435885055527875638067068241913490528696142839860698360652988701177
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_fs_sup/latest/run.log

  UVM_FATAL @ 6217.9 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_filesystem_support_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000e78
  UVM_INFO @ 6217.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_write_word_sweep_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 1 failures:
- Test flash_ctrl_write_word_sweep has 1 failures.
  - 0.flash_ctrl_write_word_sweep.9891769342676911170368288228416689612352886997956302038846426159829420834506
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_write_word_sweep/latest/run.log
```
  UVM_ERROR @ 18915.8 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_write_word_sweep_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 18915.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_oversize_error_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_oversize_error has 1 failures.
  - 0.flash_ctrl_oversize_error.25618547353485948433734010224822706171796196026280676420868348446555798821966
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_oversize_error/latest/run.log
```
  UVM_FATAL @ 18777.4 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_oversize_error_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000017f0
  UVM_INFO @ 18777.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_oversize_error_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 1 failures:
- Test flash_ctrl_oversize_error has 1 failures.
  - 1.flash_ctrl_oversize_error.71755292667982149346344919355949705630031261156809387321575981727339428920691
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_oversize_error/latest/run.log
```
  UVM_ERROR @ 151607.6 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_oversize_error_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 151607.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_common_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 1 failures:
- Test flash_ctrl_sec_cm has 1 failures.
  - 1.flash_ctrl_sec_cm.35644124550656476453975746682049906825542369473349237154309822919498703655969
    Line 299, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @ 21827.6 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 21827.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_access_after_disable_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_access_after_disable has 1 failures.
  - 1.flash_ctrl_access_after_disable.3497275038383386387128569499805963353980802455398245257490576381505597062777
    Line 288, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_access_after_disable/latest/run.log
```
  UVM_FATAL @ 14823.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_access_after_disable_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001cc8
  UVM_INFO @ 14823.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_access_after_disable_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 1 failures:
- Test flash_ctrl_access_after_disable has 1 failures.
  - 2.flash_ctrl_access_after_disable.71345064202735842269405610209830632728423339228028907072649986182621031590084
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_access_after_disable/latest/run.log
```
  UVM_ERROR @ 5559.1 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_access_after_disable_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 5559.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_common_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_sec_cm has 1 failures.
  - 3.flash_ctrl_sec_cm.47230560568092290710459016570274137120468339199165053515160254760772964257971
    Line 298, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_sec_cm/latest/run.log
```
  UVM_FATAL @ 7806.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001408
  UVM_INFO @ 7806.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_ro has 1 failures.
  - 19.flash_ctrl_ro.62499941932868740773766629772709526655353797149217537889978093890154025698197
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_ro/latest/run.log
```
  UVM_ERROR @ 659912.5 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 659912.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_disable_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_disable has 1 failures.
  - 43.flash_ctrl_disable.8173935796685843664291975500020593514904591982381757009770564940662815914677
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/43.flash_ctrl_disable/latest/run.log
```
  UVM_FATAL @ 5691.7 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000a10
  UVM_INFO @ 5691.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```