FLASH_CTRL Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: d0c52cdadd

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke flash_ctrl_smoke 3.544m 106.103us 50 50 100.00
V1 smoke_hw flash_ctrl_smoke_hw 26.110s 19.617us 5 5 100.00
V1 csr_hw_reset flash_ctrl_csr_hw_reset 38.900s 190.163us 5 5 100.00
V1 csr_rw flash_ctrl_csr_rw 17.730s 96.094us 20 20 100.00
V1 csr_bit_bash flash_ctrl_csr_bit_bash 55.950s 9.118ms 5 5 100.00
V1 csr_aliasing flash_ctrl_csr_aliasing 1.084m 2.125ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset flash_ctrl_csr_mem_rw_with_rand_reset 20.260s 588.300us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr flash_ctrl_csr_rw 17.730s 96.094us 20 20 100.00
flash_ctrl_csr_aliasing 1.084m 2.125ms 5 5 100.00
V1 mem_walk flash_ctrl_mem_walk 13.550s 29.223us 5 5 100.00
V1 mem_partial_access flash_ctrl_mem_partial_access 14.170s 27.892us 5 5 100.00
V1 TOTAL 120 120 100.00
V2 sw_op flash_ctrl_sw_op 26.890s 230.168us 5 5 100.00
V2 host_read_direct flash_ctrl_host_dir_rd 1.873m 237.827us 5 5 100.00
V2 rma_hw_if flash_ctrl_hw_rma 34.689m 340.359ms 3 3 100.00
flash_ctrl_hw_rma_reset 19.019m 350.262ms 20 20 100.00
flash_ctrl_lcmgr_intg 13.950s 15.739us 20 20 100.00
V2 host_controller_arb flash_ctrl_host_ctrl_arb 49.953m 296.368ms 5 5 100.00
V2 erase_suspend flash_ctrl_erase_suspend 7.986m 13.490ms 5 5 100.00
V2 program_reset flash_ctrl_prog_reset 16.010s 151.762us 6 30 20.00
V2 full_memory_access flash_ctrl_full_mem_access 1.148h 175.099ms 5 5 100.00
V2 rd_buff_eviction flash_ctrl_rd_buff_evict 2.481m 7.043ms 5 5 100.00
V2 rd_buff_eviction_w_ecc flash_ctrl_rw_evict 31.570s 37.651us 7 40 17.50
flash_ctrl_rw_evict_all_en 31.710s 7.832us 8 40 20.00
flash_ctrl_re_evict 38.460s 413.801us 20 20 100.00
V2 host_arb flash_ctrl_phy_arb 10.215m 2.129ms 20 20 100.00
V2 host_interleave flash_ctrl_phy_arb 10.215m 2.129ms 20 20 100.00
V2 memory_protection flash_ctrl_mp_regions 22.064m 131.438ms 20 20 100.00
V2 fetch_code flash_ctrl_fetch_code 28.200s 1.308ms 10 10 100.00
V2 all_partitions flash_ctrl_rand_ops 23.378m 469.916us 20 20 100.00
V2 error_mp flash_ctrl_error_mp 44.067m 15.612ms 10 10 100.00
V2 error_prog_win flash_ctrl_error_prog_win 17.188m 407.758us 10 10 100.00
V2 error_prog_type flash_ctrl_error_prog_type 44.281m 10.531ms 5 5 100.00
V2 error_read_seed flash_ctrl_hw_read_seed_err 13.590s 67.388us 20 20 100.00
V2 read_write_overflow flash_ctrl_oversize_error 29.880s 47.563us 0 5 0.00
V2 flash_ctrl_disable flash_ctrl_disable 22.460s 61.833us 32 50 64.00
V2 flash_ctrl_connect flash_ctrl_connect 16.150s 23.889us 80 80 100.00
V2 stress_all flash_ctrl_stress_all 27.170m 530.205us 5 5 100.00
V2 secret_partition flash_ctrl_hw_sec_otp 3.656m 11.607ms 50 50 100.00
flash_ctrl_otp_reset 2.289m 147.294us 80 80 100.00
V2 isolation_partition flash_ctrl_hw_rma 34.689m 340.359ms 3 3 100.00
V2 interrupts flash_ctrl_intr_rd 3.722m 1.364ms 40 40 100.00
flash_ctrl_intr_wr 19.050s 327.833us 0 10 0.00
flash_ctrl_intr_rd_slow_flash 4.847m 37.636ms 40 40 100.00
flash_ctrl_intr_wr_slow_flash 25.450s 4.674ms 0 10 0.00
V2 invalid_op flash_ctrl_invalid_op 1.548m 34.811ms 20 20 100.00
V2 mid_op_rst flash_ctrl_mid_op_rst 1.258m 2.571ms 5 5 100.00
V2 double_bit_err flash_ctrl_read_word_sweep_derr 23.600s 37.050us 5 5 100.00
flash_ctrl_ro_derr 2.874m 13.980ms 10 10 100.00
flash_ctrl_rw_derr 3.627m 1.162ms 0 10 0.00
flash_ctrl_derr_detect 1.014m 76.884us 0 5 0.00
flash_ctrl_integrity 3.740m 794.559us 0 5 0.00
V2 single_bit_err flash_ctrl_read_word_sweep_serr 23.330s 80.720us 5 5 100.00
flash_ctrl_ro_serr 2.440m 3.137ms 10 10 100.00
flash_ctrl_rw_serr 3.853m 3.923ms 0 10 0.00
V2 singlebit_err_counter flash_ctrl_serr_counter 1.302m 792.712us 0 5 0.00
V2 singlebit_err_address flash_ctrl_serr_address 1.410m 2.542ms 1 5 20.00
V2 scramble flash_ctrl_wo 4.345m 23.729ms 20 20 100.00
flash_ctrl_write_word_sweep 13.290s 4.911us 0 1 0.00
flash_ctrl_read_word_sweep 13.610s 48.228us 1 1 100.00
flash_ctrl_ro 2.404m 14.169ms 19 20 95.00
flash_ctrl_rw 11.069m 18.797ms 19 20 95.00
V2 filesystem_support flash_ctrl_fs_sup 40.680s 4.092ms 2 5 40.00
V2 rma_write_process_error flash_ctrl_rma_err 17.997m 303.101ms 3 3 100.00
flash_ctrl_hw_prog_rma_wipe_err 5.123m 10.012ms 20 20 100.00
V2 alert_test flash_ctrl_alert_test 14.470s 57.493us 50 50 100.00
V2 intr_test flash_ctrl_intr_test 14.150s 111.936us 50 50 100.00
V2 tl_d_oob_addr_access flash_ctrl_tl_errors 20.390s 227.068us 20 20 100.00
V2 tl_d_illegal_access flash_ctrl_tl_errors 20.390s 227.068us 20 20 100.00
V2 tl_d_outstanding_access flash_ctrl_csr_hw_reset 38.900s 190.163us 5 5 100.00
flash_ctrl_csr_rw 17.730s 96.094us 20 20 100.00
flash_ctrl_csr_aliasing 1.084m 2.125ms 5 5 100.00
flash_ctrl_same_csr_outstanding 35.600s 330.969us 20 20 100.00
V2 tl_d_partial_access flash_ctrl_csr_hw_reset 38.900s 190.163us 5 5 100.00
flash_ctrl_csr_rw 17.730s 96.094us 20 20 100.00
flash_ctrl_csr_aliasing 1.084m 2.125ms 5 5 100.00
flash_ctrl_same_csr_outstanding 35.600s 330.969us 20 20 100.00
V2 TOTAL 836 1013 82.53
V2S shadow_reg_update_error flash_ctrl_shadow_reg_errors 16.210s 51.302us 20 20 100.00
V2S shadow_reg_read_clear_staged_value flash_ctrl_shadow_reg_errors 16.210s 51.302us 20 20 100.00
V2S shadow_reg_storage_error flash_ctrl_shadow_reg_errors 16.210s 51.302us 20 20 100.00
V2S shadowed_reset_glitch flash_ctrl_shadow_reg_errors 16.210s 51.302us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw flash_ctrl_shadow_reg_errors_with_csr_rw 16.140s 14.612us 20 20 100.00
V2S tl_intg_err flash_ctrl_sec_cm 44.170s 35.241us 0 5 0.00
flash_ctrl_tl_intg_err 15.432m 640.349us 20 20 100.00
V2S sec_cm_reg_bus_integrity flash_ctrl_tl_intg_err 15.432m 640.349us 20 20 100.00
V2S sec_cm_host_bus_integrity flash_ctrl_tl_intg_err 15.432m 640.349us 20 20 100.00
V2S sec_cm_mem_bus_integrity flash_ctrl_rd_intg 33.120s 63.970us 3 3 100.00
flash_ctrl_wr_intg 14.900s 81.275us 3 3 100.00
V2S sec_cm_scramble_key_sideload flash_ctrl_smoke 3.544m 106.103us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi flash_ctrl_otp_reset 2.289m 147.294us 80 80 100.00
flash_ctrl_disable 22.460s 61.833us 32 50 64.00
flash_ctrl_sec_info_access 1.795m 43.192ms 50 50 100.00
flash_ctrl_connect 16.150s 23.889us 80 80 100.00
V2S sec_cm_ctrl_config_regwen flash_ctrl_config_regwen 14.130s 46.225us 5 5 100.00
V2S sec_cm_data_regions_config_regwen flash_ctrl_csr_rw 17.730s 96.094us 20 20 100.00
V2S sec_cm_data_regions_config_shadow flash_ctrl_shadow_reg_errors 16.210s 51.302us 20 20 100.00
V2S sec_cm_info_regions_config_regwen flash_ctrl_csr_rw 17.730s 96.094us 20 20 100.00
V2S sec_cm_info_regions_config_shadow flash_ctrl_shadow_reg_errors 16.210s 51.302us 20 20 100.00
V2S sec_cm_bank_config_regwen flash_ctrl_csr_rw 17.730s 96.094us 20 20 100.00
V2S sec_cm_bank_config_shadow flash_ctrl_shadow_reg_errors 16.210s 51.302us 20 20 100.00
V2S sec_cm_mem_ctrl_global_esc flash_ctrl_disable 22.460s 61.833us 32 50 64.00
V2S sec_cm_mem_ctrl_local_esc flash_ctrl_rd_intg 33.120s 63.970us 3 3 100.00
flash_ctrl_access_after_disable 13.610s 48.150us 1 3 33.33
V2S sec_cm_mem_disable_config_mubi flash_ctrl_disable 22.460s 61.833us 32 50 64.00
V2S sec_cm_exec_config_redun flash_ctrl_fetch_code 28.200s 1.308ms 10 10 100.00
V2S sec_cm_mem_scramble flash_ctrl_rw 11.069m 18.797ms 19 20 95.00
V2S sec_cm_mem_integrity flash_ctrl_rw_serr 3.853m 3.923ms 0 10 0.00
flash_ctrl_rw_derr 3.627m 1.162ms 0 10 0.00
flash_ctrl_integrity 3.740m 794.559us 0 5 0.00
V2S sec_cm_rma_entry_mem_sec_wipe flash_ctrl_hw_rma 34.689m 340.359ms 3 3 100.00
V2S sec_cm_ctrl_fsm_sparse flash_ctrl_sec_cm 44.170s 35.241us 0 5 0.00
V2S sec_cm_phy_fsm_sparse flash_ctrl_sec_cm 44.170s 35.241us 0 5 0.00
V2S sec_cm_phy_prog_fsm_sparse flash_ctrl_sec_cm 44.170s 35.241us 0 5 0.00
V2S sec_cm_ctr_redun flash_ctrl_sec_cm 44.170s 35.241us 0 5 0.00
V2S sec_cm_phy_arbiter_ctrl_redun flash_ctrl_phy_arb_redun 23.420s 895.847us 5 5 100.00
V2S sec_cm_phy_host_grant_ctrl_consistency flash_ctrl_phy_host_grant_err 14.380s 98.700us 5 5 100.00
V2S sec_cm_phy_ack_ctrl_consistency flash_ctrl_phy_ack_consistency 16.230s 75.167us 5 5 100.00
V2S sec_cm_fifo_ctr_redun flash_ctrl_sec_cm 44.170s 35.241us 0 5 0.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse flash_ctrl_sec_cm 44.170s 35.241us 0 5 0.00
V2S sec_cm_prog_tl_lc_gate_fsm_sparse flash_ctrl_sec_cm 44.170s 35.241us 0 5 0.00
V2S TOTAL 137 144 95.14
V3 asymmetric_read_path flash_ctrl_rd_ooo 48.020s 543.129us 1 1 100.00
V3 stress_all_with_rand_reset flash_ctrl_stress_all_with_rand_reset 0 0 --
V3 TOTAL 1 1 100.00
TOTAL 1094 1278 85.60

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 55 55 38 69.09
V2S 12 12 10 83.33
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
95.01 95.85 93.45 94.81 90.48 98.07 94.61 97.78

Failure Buckets

Past Results