FLASH_CTRL Simulation Results

Sunday May 05 2024 19:05:13 UTC

GitHub Revision: `d0c52cdadd`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 81579111587980121648949789282063322266496016209500883225240730864920651071561

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	3.544m	106.103us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.110s	19.617us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	38.900s	190.163us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.730s	96.094us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	55.950s	9.118ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.084m	2.125ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	20.260s	588.300us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.730s	96.094us	20	20	100.00
		flash_ctrl_csr_aliasing	1.084m	2.125ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.550s	29.223us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.170s	27.892us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.890s	230.168us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	1.873m	237.827us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	34.689m	340.359ms	3	3	100.00
		flash_ctrl_hw_rma_reset	19.019m	350.262ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.950s	15.739us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	49.953m	296.368ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	7.986m	13.490ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	16.010s	151.762us	6	30	20.00
V2	full_memory_access	flash_ctrl_full_mem_access	1.148h	175.099ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.481m	7.043ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	31.570s	37.651us	7	40	17.50
		flash_ctrl_rw_evict_all_en	31.710s	7.832us	8	40	20.00
		flash_ctrl_re_evict	38.460s	413.801us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	10.215m	2.129ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	10.215m	2.129ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	22.064m	131.438ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	28.200s	1.308ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	23.378m	469.916us	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	44.067m	15.612ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.188m	407.758us	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	44.281m	10.531ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	13.590s	67.388us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	29.880s	47.563us	0	5	0.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.460s	61.833us	32	50	64.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.150s	23.889us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	27.170m	530.205us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	3.656m	11.607ms	50	50	100.00
		flash_ctrl_otp_reset	2.289m	147.294us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	34.689m	340.359ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	3.722m	1.364ms	40	40	100.00
		flash_ctrl_intr_wr	19.050s	327.833us	0	10	0.00
		flash_ctrl_intr_rd_slow_flash	4.847m	37.636ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	25.450s	4.674ms	0	10	0.00
V2	invalid_op	flash_ctrl_invalid_op	1.548m	34.811ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.258m	2.571ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	23.600s	37.050us	5	5	100.00
		flash_ctrl_ro_derr	2.874m	13.980ms	10	10	100.00
		flash_ctrl_rw_derr	3.627m	1.162ms	0	10	0.00
		flash_ctrl_derr_detect	1.014m	76.884us	0	5	0.00
		flash_ctrl_integrity	3.740m	794.559us	0	5	0.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	23.330s	80.720us	5	5	100.00
		flash_ctrl_ro_serr	2.440m	3.137ms	10	10	100.00
		flash_ctrl_rw_serr	3.853m	3.923ms	0	10	0.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.302m	792.712us	0	5	0.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.410m	2.542ms	1	5	20.00
V2	scramble	flash_ctrl_wo	4.345m	23.729ms	20	20	100.00
		flash_ctrl_write_word_sweep	13.290s	4.911us	0	1	0.00
		flash_ctrl_read_word_sweep	13.610s	48.228us	1	1	100.00
		flash_ctrl_ro	2.404m	14.169ms	19	20	95.00
		flash_ctrl_rw	11.069m	18.797ms	19	20	95.00
V2	filesystem_support	flash_ctrl_fs_sup	40.680s	4.092ms	2	5	40.00
V2	rma_write_process_error	flash_ctrl_rma_err	17.997m	303.101ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	5.123m	10.012ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.470s	57.493us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.150s	111.936us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.390s	227.068us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.390s	227.068us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	38.900s	190.163us	5	5	100.00
		flash_ctrl_csr_rw	17.730s	96.094us	20	20	100.00
		flash_ctrl_csr_aliasing	1.084m	2.125ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.600s	330.969us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	38.900s	190.163us	5	5	100.00
		flash_ctrl_csr_rw	17.730s	96.094us	20	20	100.00
		flash_ctrl_csr_aliasing	1.084m	2.125ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.600s	330.969us	20	20	100.00
V2		TOTAL			836	1013	82.53
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.210s	51.302us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.210s	51.302us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.210s	51.302us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.210s	51.302us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.140s	14.612us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	44.170s	35.241us	0	5	0.00
		flash_ctrl_tl_intg_err	15.432m	640.349us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.432m	640.349us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.432m	640.349us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	33.120s	63.970us	3	3	100.00
		flash_ctrl_wr_intg	14.900s	81.275us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	3.544m	106.103us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.289m	147.294us	80	80	100.00
		flash_ctrl_disable	22.460s	61.833us	32	50	64.00
		flash_ctrl_sec_info_access	1.795m	43.192ms	50	50	100.00
		flash_ctrl_connect	16.150s	23.889us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.130s	46.225us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.730s	96.094us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.210s	51.302us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.730s	96.094us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.210s	51.302us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.730s	96.094us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.210s	51.302us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.460s	61.833us	32	50	64.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	33.120s	63.970us	3	3	100.00
		flash_ctrl_access_after_disable	13.610s	48.150us	1	3	33.33
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.460s	61.833us	32	50	64.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	28.200s	1.308ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	11.069m	18.797ms	19	20	95.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	3.853m	3.923ms	0	10	0.00
		flash_ctrl_rw_derr	3.627m	1.162ms	0	10	0.00
		flash_ctrl_integrity	3.740m	794.559us	0	5	0.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	34.689m	340.359ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	44.170s	35.241us	0	5	0.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	44.170s	35.241us	0	5	0.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	44.170s	35.241us	0	5	0.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	44.170s	35.241us	0	5	0.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	23.420s	895.847us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.380s	98.700us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	16.230s	75.167us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	44.170s	35.241us	0	5	0.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	44.170s	35.241us	0	5	0.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	44.170s	35.241us	0	5	0.00
V2S		TOTAL			137	144	95.14
V3	asymmetric_read_path	flash_ctrl_rd_ooo	48.020s	543.129us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1094	1278	85.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	38	69.09
V2S	12	12	10	83.33
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.01	95.85	93.45	94.81	90.48	98.07	94.61	97.78

Failure Buckets

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 42 failures:

Test flash_ctrl_rw_evict_all_en has 22 failures.

1.flash_ctrl_rw_evict_all_en.39002534892510721381682736775589237119695317963142672382297986137939580326007
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 43414.9 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 43414.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_rw_evict_all_en.71353063659081629721299619109618410470210750967276113402158030877252373905567
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 15961.2 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 15961.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 20 more failures.

Test flash_ctrl_rw_evict has 20 failures.

3.flash_ctrl_rw_evict.94038565608397111862377786467275767229258057452335588782278762947535194165375
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 31678.3 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 31678.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.flash_ctrl_rw_evict.98705879796249049171465567969368393393605569126126914216780203091687371776614
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 9735.8 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 9735.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 18 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 25 failures:

Test flash_ctrl_rw_serr has 10 failures.

0.flash_ctrl_rw_serr.101327162605075590131037314152203080091125385885881831809040245712101432983980
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest/run.log

  UVM_FATAL @ 3922912.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00002538
  UVM_INFO @ 3922912.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_rw_serr.69470854368190724844378700732015897577814422943167291001681526634379001150370
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log

  UVM_FATAL @ 457669.6 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000bd9b0
  UVM_INFO @ 457669.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test flash_ctrl_rw_derr has 10 failures.

0.flash_ctrl_rw_derr.23037812631265362748377208627116050068468356531417194028079380591757349241584
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest/run.log

  UVM_FATAL @ 1093111.9 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00002568
  UVM_INFO @ 1093111.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_rw_derr.84161233116855699537246800869386070863413302504918810799879114600584241721940
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log

  UVM_FATAL @ 838282.0 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000025c8
  UVM_INFO @ 838282.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test flash_ctrl_integrity has 5 failures.

0.flash_ctrl_integrity.106067220110694521256889131136700835048096182339273824972343389613289926060219
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log

  UVM_FATAL @ 3295972.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000034e8
  UVM_INFO @ 3295972.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_integrity.115500886864222695187148238418965711011704658278762691219647954967049678524490
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log

  UVM_FATAL @ 550069.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00004fb8
  UVM_INFO @ 550069.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_rw_evict_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 19 failures:

Test flash_ctrl_rw_evict has 11 failures.

0.flash_ctrl_rw_evict.46988078618172893116806122354127567527703866204068307229530934374522603498167
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 10179.4 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 10179.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_rw_evict.109209975542274181139930960781898866097831049222384932567831658561858566690710
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 89587.5 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 89587.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

Test flash_ctrl_rw_evict_all_en has 8 failures.

8.flash_ctrl_rw_evict_all_en.87686924056801688987864058401654956939787240702665252063548871936434555561973
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 19622.6 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 19622.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.flash_ctrl_rw_evict_all_en.54885469208136930623397186571259395578371725330270251540114958946434496072249
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 18335.2 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 18335.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 18 failures:

Test flash_ctrl_intr_wr has 8 failures.

0.flash_ctrl_intr_wr.48854830157763004388242739329084098082982611642017843721829491662802623023984
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr/latest/run.log

  UVM_ERROR @ 327832.9 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 327832.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_intr_wr.36482962601925200475620254331344838946653702816723881105367801739886491555024
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr/latest/run.log

  UVM_ERROR @ 666965.1 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 666965.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 6 more failures.

Test flash_ctrl_intr_wr_slow_flash has 10 failures.

0.flash_ctrl_intr_wr_slow_flash.30662029042557194634829519737472209728304664000248650490909817747933595052153
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr_slow_flash/latest/run.log

  UVM_ERROR @ 20322.8 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 20322.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_intr_wr_slow_flash.52033563100688084369770988829347300790456412110952603336571470289225089459560
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr_slow_flash/latest/run.log

  UVM_ERROR @ 4673674.9 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 4673674.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_prog_reset_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 15 failures:

Test flash_ctrl_prog_reset has 15 failures.

2.flash_ctrl_prog_reset.48400256727407910322232148937696004925212971744749420541377076881657375422683
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_prog_reset/latest/run.log

  UVM_ERROR @ 151762.0 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 151762.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.flash_ctrl_prog_reset.48448567975353950467778846494149164852573664036241232143851632748436573824944
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_prog_reset/latest/run.log

  UVM_ERROR @ 9064.4 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 9064.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 13 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_disable_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 13 failures:

Test flash_ctrl_disable has 13 failures.

5.flash_ctrl_disable.85946345047962900222554584632423888138528702891950074723217281667210728480675
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 8818.1 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 8818.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.flash_ctrl_disable.7000018450644298880481659172365308667035455170770309343902351392871467263514
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 4439.3 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 4439.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_prog_reset_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 7 failures:
- Test flash_ctrl_prog_reset has 7 failures.
  - 1.flash_ctrl_prog_reset.104669267139054645070014899331643448664709732845678920285999740135898312658746
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_prog_reset/latest/run.log
```
  UVM_ERROR @ 41259.5 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 41259.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 3.flash_ctrl_prog_reset.14773779451200796741183670944215406912883759255043830986465130639477174616085
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_prog_reset/latest/run.log
```
  UVM_ERROR @ 19922.0 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 19922.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 5 more failures.
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_serr_counter_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 5 failures:
- Test flash_ctrl_serr_counter has 5 failures.
  - 0.flash_ctrl_serr_counter.32318712949073373930726524960041709367739776850023900340701633322935786340520
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_serr_counter/latest/run.log
```
  UVM_FATAL @ 1153723.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_counter_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000013d0
  UVM_INFO @ 1153723.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.flash_ctrl_serr_counter.45176339515413830608014107911498281058627931022380052621318265663553463343890
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_serr_counter/latest/run.log
```
  UVM_FATAL @ 418060.7 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_counter_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00003e50
  UVM_INFO @ 418060.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_derr_detect_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 5 failures:

Test flash_ctrl_derr_detect has 5 failures.

0.flash_ctrl_derr_detect.80733023119684706185339405446274734610769866855040542364899671005753398062549
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log

  UVM_ERROR @ 4529.8 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_derr_detect_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 4529.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_derr_detect.83643101682088751545550816569772386380592127114786232979911612201226130981656
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log

  UVM_ERROR @ 29694.6 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_derr_detect_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 29694.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_disable_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 5 failures:
- Test flash_ctrl_disable has 5 failures.
  - 0.flash_ctrl_disable.83038401118440071968487722140230722253240364982227874358424336319826588076239
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_disable/latest/run.log
```
  UVM_ERROR @ 19779.6 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 19779.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.flash_ctrl_disable.64398877633386967037030038746203428356780661839449866542462229837321228939065
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_disable/latest/run.log
```
  UVM_ERROR @ 10821.6 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 10821.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_serr_address_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 4 failures:
- Test flash_ctrl_serr_address has 4 failures.
  - 1.flash_ctrl_serr_address.4541862498949768995187876979211658200069165762910831293239280039518404765723
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_serr_address/latest/run.log
```
  UVM_FATAL @ 1163156.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_address_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00003020
  UVM_INFO @ 1163156.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.flash_ctrl_serr_address.30671388293379112253531284030804257731125948585993093805110508906651710601952
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_serr_address/latest/run.log
```
  UVM_FATAL @ 18971.7 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_address_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000800
  UVM_INFO @ 18971.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 4 failures:

Test flash_ctrl_rw_evict has 2 failures.

5.flash_ctrl_rw_evict.84894017284238980899793202050659356960451113279200883595340280623141915170369
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 22637.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000029f0
  UVM_INFO @ 22637.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

22.flash_ctrl_rw_evict.70452930054341779564842296232774422647981296534733429840746504094516538360405
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 9777.8 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000017c8
  UVM_INFO @ 9777.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test flash_ctrl_rw_evict_all_en has 2 failures.

22.flash_ctrl_rw_evict_all_en.93081694612545489797241416408836882535315104491017096517430097634405285246061
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 18042.9 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001258
  UVM_INFO @ 18042.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

27.flash_ctrl_rw_evict_all_en.25526733810529037879623599180489258035964218148958004161868871287847566062333
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 7807.9 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000015b8
  UVM_INFO @ 7807.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_oversize_error_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 3 failures:
- Test flash_ctrl_oversize_error has 3 failures.
  - 0.flash_ctrl_oversize_error.45578878884738354393328376932674264544350382111327047840737893802882072209335
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_oversize_error/latest/run.log
```
  UVM_ERROR @ 13725.5 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_oversize_error_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 13725.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.flash_ctrl_oversize_error.33744899607221204842508695114370101824104055764594881363480754570797714257483
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_oversize_error/latest/run.log
```
  UVM_ERROR @ 47563.0 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_oversize_error_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 47563.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_filesystem_support_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 3 failures:

Test flash_ctrl_fs_sup has 3 failures.

0.flash_ctrl_fs_sup.26727059862298931707645561686614197632341141449253413414855649890611602367553
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_fs_sup/latest/run.log

  UVM_FATAL @ 11784.5 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_filesystem_support_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000008f0
  UVM_INFO @ 11784.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_fs_sup.28784403405061826267475414724987398861386824978032611426540502784818181854842
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_fs_sup/latest/run.log

  UVM_FATAL @ 126500.9 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_filesystem_support_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000016f0
  UVM_INFO @ 126500.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_common_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 2 failures:
- Test flash_ctrl_sec_cm has 2 failures.
  - 0.flash_ctrl_sec_cm.60752357943197716466644064361027480077640919101212695923522718472221974772148
    Line 288, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @ 2980.8 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 2980.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.flash_ctrl_sec_cm.95646908778507840586940800305093770237312733419279097069104530766411127031600
    Line 345, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @ 35241.4 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 35241.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_common_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 2 failures:

Test flash_ctrl_sec_cm has 2 failures.

1.flash_ctrl_sec_cm.67118379299163805687430124982242351446900807852256614638160794408772312348707
Line 365, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_sec_cm/latest/run.log

  UVM_ERROR @ 15682.2 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 15682.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_sec_cm.86228613580185056301135735563422124007318153421316154551879083007884938089775
Line 298, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_sec_cm/latest/run.log

  UVM_ERROR @ 26185.8 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 26185.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_oversize_error_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 2 failures:

Test flash_ctrl_oversize_error has 2 failures.

3.flash_ctrl_oversize_error.76946139431308541254772844021373812477802193051552352752994682716134751914652
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_oversize_error/latest/run.log

  UVM_ERROR @ 108162.9 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_oversize_error_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 108162.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.flash_ctrl_oversize_error.95789200575882599978895138164074018612533626792080687257983640979509390610541
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_oversize_error/latest/run.log

  UVM_ERROR @ 9094.8 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_oversize_error_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 9094.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_prog_reset_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 2 failures:
- Test flash_ctrl_prog_reset has 2 failures.
  - 4.flash_ctrl_prog_reset.92861681407586899629351919160009837724304215645457713927910766134680989998007
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_prog_reset/latest/run.log
```
  UVM_FATAL @ 9842.0 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000008f0
  UVM_INFO @ 9842.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 24.flash_ctrl_prog_reset.54700278631405032975496017739682314662029778349726708594789961860782065449375
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/24.flash_ctrl_prog_reset/latest/run.log
```
  UVM_FATAL @ 16521.6 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000019a8
  UVM_INFO @ 16521.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_intr_wr_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 2 failures:

Test flash_ctrl_intr_wr has 2 failures.

8.flash_ctrl_intr_wr.32090231954216823385262654978992159839504294618914731640494434579409932620450
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr/latest/run.log

  UVM_FATAL @ 11193.0 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000ff0
  UVM_INFO @ 11193.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.flash_ctrl_intr_wr.57594841379678041896622599226395397765876949291656003104367460127569886011106
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr/latest/run.log

  UVM_FATAL @ 51580.6 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001998
  UVM_INFO @ 51580.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:
- Test flash_ctrl_rw has 1 failures.
  - 10.flash_ctrl_rw.70793898702614463904481101778341497781516990002844294644498324004527356146720
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/10.flash_ctrl_rw/latest/run.log
```
  UVM_ERROR @ 1360106.4 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 1360106.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test flash_ctrl_ro has 1 failures.
  - 16.flash_ctrl_ro.22338560148379699727066686526332083832345770537116681964134983537707348983096
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/16.flash_ctrl_ro/latest/run.log
```
  UVM_ERROR @ 9471.7 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 9471.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_write_word_sweep_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 1 failures:
- Test flash_ctrl_write_word_sweep has 1 failures.
  - 0.flash_ctrl_write_word_sweep.105302212971350521743851413486685117771052201406647255306114866360398783113466
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_write_word_sweep/latest/run.log
```
  UVM_ERROR @ 4911.3 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_write_word_sweep_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 4911.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_access_after_disable_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 1 failures:
- Test flash_ctrl_access_after_disable has 1 failures.
  - 0.flash_ctrl_access_after_disable.95322620127962858022912950611523635210387095909302140211622933224119556812122
    Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_access_after_disable/latest/run.log
```
  UVM_ERROR @ 14727.7 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_access_after_disable_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 14727.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_common_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_sec_cm has 1 failures.
  - 2.flash_ctrl_sec_cm.62797242344653338787869877990749475808410419208746648109192236999915606088628
    Line 298, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_sec_cm/latest/run.log
```
  UVM_FATAL @ 5144.1 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000010f8
  UVM_INFO @ 5144.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_access_after_disable_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 1 failures:
- Test flash_ctrl_access_after_disable has 1 failures.
  - 2.flash_ctrl_access_after_disable.65968315888390365046015623165304619934568138029493553153615574689160143613368
    Line 288, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_access_after_disable/latest/run.log
```
  UVM_ERROR @ 15620.8 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_access_after_disable_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 15620.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```