FLASH_CTRL Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: `18c8953cf1`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.424m	687.661us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	26.390s	52.040us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	46.690s	253.231us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	17.680s	255.768us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.725m	45.519ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.078m	1.801ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	19.990s	45.017us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	17.680s	255.768us	20	20	100.00
		flash_ctrl_csr_aliasing	1.078m	1.801ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	13.540s	196.206us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	14.060s	53.729us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	26.170s	25.244us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	2.143m	69.271us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	32.565m	122.562ms	3	3	100.00
		flash_ctrl_hw_rma_reset	17.053m	230.214ms	20	20	100.00
		flash_ctrl_lcmgr_intg	13.790s	63.913us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	41.138m	595.731ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	9.241m	15.954ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	15.640s	32.300us	5	30	16.67
V2	full_memory_access	flash_ctrl_full_mem_access	1.180h	97.825ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	2.518m	703.482us	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	31.830s	59.152us	7	40	17.50
		flash_ctrl_rw_evict_all_en	31.690s	143.252us	8	40	20.00
		flash_ctrl_re_evict	40.150s	518.073us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	9.103m	2.790ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	9.103m	2.790ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	13.963m	33.470ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	27.000s	370.395us	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	25.037m	1.866ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	43.232m	80.527ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	17.479m	1.549ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	56.472m	4.512ms	5	5	100.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	14.160s	106.312us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	28.790s	38.853us	0	5	0.00
V2	flash_ctrl_disable	flash_ctrl_disable	22.320s	6.581us	31	50	62.00
V2	flash_ctrl_connect	flash_ctrl_connect	16.020s	25.748us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	25.770m	1.556ms	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.300m	22.953ms	50	50	100.00
		flash_ctrl_otp_reset	2.236m	92.643us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	32.565m	122.562ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.270m	4.673ms	40	40	100.00
		flash_ctrl_intr_wr	16.480s	161.689us	0	10	0.00
		flash_ctrl_intr_rd_slow_flash	5.866m	36.467ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	17.790s	3.166ms	0	10	0.00
V2	invalid_op	flash_ctrl_invalid_op	1.667m	34.406ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	1.219m	4.009ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	22.620s	62.240us	5	5	100.00
		flash_ctrl_ro_derr	3.038m	3.564ms	10	10	100.00
		flash_ctrl_rw_derr	3.729m	959.161us	0	10	0.00
		flash_ctrl_derr_detect	43.240s	39.897us	0	5	0.00
		flash_ctrl_integrity	2.152m	521.772us	0	5	0.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	22.870s	366.496us	5	5	100.00
		flash_ctrl_ro_serr	2.817m	673.725us	10	10	100.00
		flash_ctrl_rw_serr	4.783m	7.882ms	0	10	0.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.453m	2.833ms	1	5	20.00
V2	singlebit_err_address	flash_ctrl_serr_address	1.150m	2.159ms	0	5	0.00
V2	scramble	flash_ctrl_wo	4.766m	5.642ms	20	20	100.00
		flash_ctrl_write_word_sweep	13.210s	18.795us	0	1	0.00
		flash_ctrl_read_word_sweep	13.140s	54.751us	1	1	100.00
		flash_ctrl_ro	2.667m	1.377ms	19	20	95.00
		flash_ctrl_rw	12.670m	8.977ms	20	20	100.00
V2	filesystem_support	flash_ctrl_fs_sup	36.410s	789.151us	4	5	80.00
V2	rma_write_process_error	flash_ctrl_rma_err	19.125m	73.794ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	2.868m	10.020ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	14.350s	172.227us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	14.830s	27.682us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	20.320s	642.701us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	20.320s	642.701us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	46.690s	253.231us	5	5	100.00
		flash_ctrl_csr_rw	17.680s	255.768us	20	20	100.00
		flash_ctrl_csr_aliasing	1.078m	1.801ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.460s	220.321us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	46.690s	253.231us	5	5	100.00
		flash_ctrl_csr_rw	17.680s	255.768us	20	20	100.00
		flash_ctrl_csr_aliasing	1.078m	1.801ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	35.460s	220.321us	20	20	100.00
V2		TOTAL			837	1013	82.63
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	16.350s	14.653us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	16.350s	14.653us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	16.350s	14.653us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	16.350s	14.653us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	16.270s	12.411us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	43.680s	39.936us	0	5	0.00
		flash_ctrl_tl_intg_err	15.243m	910.930us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	15.243m	910.930us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	15.243m	910.930us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	32.610s	543.039us	3	3	100.00
		flash_ctrl_wr_intg	14.880s	157.250us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.424m	687.661us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	2.236m	92.643us	80	80	100.00
		flash_ctrl_disable	22.320s	6.581us	31	50	62.00
		flash_ctrl_sec_info_access	1.460m	3.467ms	50	50	100.00
		flash_ctrl_connect	16.020s	25.748us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	14.260s	38.795us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	17.680s	255.768us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.350s	14.653us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	17.680s	255.768us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	16.350s	14.653us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	17.680s	255.768us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	16.350s	14.653us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	22.320s	6.581us	31	50	62.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	32.610s	543.039us	3	3	100.00
		flash_ctrl_access_after_disable	13.660s	42.571us	0	3	0.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	22.320s	6.581us	31	50	62.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	27.000s	370.395us	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	12.670m	8.977ms	20	20	100.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	4.783m	7.882ms	0	10	0.00
		flash_ctrl_rw_derr	3.729m	959.161us	0	10	0.00
		flash_ctrl_integrity	2.152m	521.772us	0	5	0.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	32.565m	122.562ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	43.680s	39.936us	0	5	0.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	43.680s	39.936us	0	5	0.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	43.680s	39.936us	0	5	0.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	43.680s	39.936us	0	5	0.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	25.660s	756.044us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	14.130s	53.094us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	14.420s	15.609us	5	5	100.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	43.680s	39.936us	0	5	0.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	43.680s	39.936us	0	5	0.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	43.680s	39.936us	0	5	0.00
V2S		TOTAL			136	144	94.44
V3	asymmetric_read_path	flash_ctrl_rd_ooo	48.060s	339.845us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1094	1278	85.60

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	39	70.91
V2S	12	12	10	83.33
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.90	95.81	93.39	94.81	89.80	98.03	94.61	97.87

Failure Buckets

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 35 failures:

Test flash_ctrl_rw_evict_all_en has 17 failures.

1.flash_ctrl_rw_evict_all_en.62722774004050700527160949582518091885146261012220041744837145165440490880078
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 44955.1 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 44955.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.flash_ctrl_rw_evict_all_en.32685592929825318364042595522870169878949991494322306850609344415709545966400
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 41730.8 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 41730.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 15 more failures.

Test flash_ctrl_rw_evict has 18 failures.

5.flash_ctrl_rw_evict.14073275283165739958513632906265690715465583685890495805449218991392755960006
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 13943.8 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 13943.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.flash_ctrl_rw_evict.33099997665191193315647914423527420216308866472248772477857989228115504663508
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 17424.0 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 17424.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 16 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 25 failures:

Test flash_ctrl_rw_serr has 10 failures.

0.flash_ctrl_rw_serr.94614313033466307956032178322567769876950623656099066676010806806242357231551
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest/run.log

  UVM_FATAL @ 129379.6 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000f98
  UVM_INFO @ 129379.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_rw_serr.27794154822361834617125804359148056704884874492662581566114926416953861423057
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest/run.log

  UVM_FATAL @ 316748.0 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000048c0
  UVM_INFO @ 316748.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test flash_ctrl_rw_derr has 10 failures.

0.flash_ctrl_rw_derr.98400759685847517882397351777243753509532204823779001428452756776491085338291
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest/run.log

  UVM_FATAL @ 826725.5 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00002ea8
  UVM_INFO @ 826725.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_rw_derr.24191800933250676334969833704289833000061967468386945908605824722240408686316
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest/run.log

  UVM_FATAL @ 815679.5 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000045e0
  UVM_INFO @ 815679.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test flash_ctrl_integrity has 5 failures.

0.flash_ctrl_integrity.1815817711032298001919708293583341745850975054814609155685017149801918517998
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest/run.log

  UVM_FATAL @ 784350.7 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00002468
  UVM_INFO @ 784350.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_integrity.109014965104991875898623103776582957522316833246969635952514946979751975458669
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest/run.log

  UVM_FATAL @ 783744.7 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000480
  UVM_INFO @ 783744.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_rw_evict_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 22 failures:

Test flash_ctrl_rw_evict has 10 failures.

0.flash_ctrl_rw_evict.48903023226428803858647630761154286770870523081662662193339568613082181431936
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 31162.2 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 31162.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_rw_evict.8857085736217488210708209928042373764297322683298864958439366895493341616103
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest/run.log

  UVM_ERROR @ 17288.4 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 17288.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test flash_ctrl_rw_evict_all_en has 12 failures.

0.flash_ctrl_rw_evict_all_en.16174012975506420145716940422165716189224450794141246814454754260541042616187
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 8273.2 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 8273.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.flash_ctrl_rw_evict_all_en.49691454081460501928713188893199230343207313224182750561401689428571232193740
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_ERROR @ 22265.1 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 22265.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 19 failures:

Test flash_ctrl_intr_wr has 10 failures.

0.flash_ctrl_intr_wr.96683999443225241964303081411457855717667542227862466207134936420938278512360
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr/latest/run.log

  UVM_ERROR @ 9633.0 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 9633.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_intr_wr.20826378711373693509660661907518189498101977663809111617755269518742218656759
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr/latest/run.log

  UVM_ERROR @ 647532.0 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 647532.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.

Test flash_ctrl_intr_wr_slow_flash has 9 failures.

0.flash_ctrl_intr_wr_slow_flash.39428014152923349570284160140546889139186868520348645157767737594673569670490
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr_slow_flash/latest/run.log

  UVM_ERROR @ 37524.1 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 37524.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_intr_wr_slow_flash.10374789185071841732864018887997339246080305379902357992111760206182728037423
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr_slow_flash/latest/run.log

  UVM_ERROR @ 21258.3 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 21258.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 7 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_prog_reset_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 14 failures:

Test flash_ctrl_prog_reset has 14 failures.

3.flash_ctrl_prog_reset.77039609209928127502530814439801417717901027588551183499500608815109137420204
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_prog_reset/latest/run.log

  UVM_ERROR @ 9427.9 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 9427.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

4.flash_ctrl_prog_reset.99505700652645627754375480834257243968487235219483892183850473123856841056425
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_prog_reset/latest/run.log

  UVM_ERROR @ 4833.3 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 4833.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_prog_reset_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 11 failures:
- Test flash_ctrl_prog_reset has 11 failures.
  - 0.flash_ctrl_prog_reset.41114872075390033758852736955293986065679298687535750501508314680777483411095
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_prog_reset/latest/run.log
```
  UVM_ERROR @ 26075.7 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 26075.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.flash_ctrl_prog_reset.27528645925424247205826894678638660195200183255273017871823789980177316319524
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_prog_reset/latest/run.log
```
  UVM_ERROR @ 8920.4 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_prog_reset_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 8920.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 9 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 8 failures:

Test flash_ctrl_rw_evict has 5 failures.

1.flash_ctrl_rw_evict.44523711481612352126660592960698939335310807230588530657764055685455666493461
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 26078.9 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001d60
  UVM_INFO @ 26078.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.flash_ctrl_rw_evict.97240384940927692153171851355369564143344096392470422512516787038107756270746
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict/latest/run.log

  UVM_FATAL @ 9952.1 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001890
  UVM_INFO @ 9952.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test flash_ctrl_rw_evict_all_en has 3 failures.

5.flash_ctrl_rw_evict_all_en.19449006683347790805323289901159700899685332400097805149662340566244441777056
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 62664.0 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000a88
  UVM_INFO @ 62664.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

14.flash_ctrl_rw_evict_all_en.104159334164186389713019574425787817794999270430617145937330949198113462149413
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict_all_en/latest/run.log

  UVM_FATAL @ 14531.7 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_rw_evict_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000018c0
  UVM_INFO @ 14531.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_disable_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 8 failures:
- Test flash_ctrl_disable has 8 failures.
  - 9.flash_ctrl_disable.96482806307060436104769668596571454318516714317984446369955420145758941614129
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/9.flash_ctrl_disable/latest/run.log
```
  UVM_ERROR @ 7720.5 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 7720.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 13.flash_ctrl_disable.97862579396225119151401584395784643389663432681012990967613302139282312824046
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/13.flash_ctrl_disable/latest/run.log
```
  UVM_ERROR @ 18151.6 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 18151.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 6 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_disable_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 6 failures:

Test flash_ctrl_disable has 6 failures.

1.flash_ctrl_disable.112740262395757870545602583385899988920162802791220224175617879555379907376386
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 5742.3 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 5742.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

19.flash_ctrl_disable.31045205948631783923001474384403582939016992557063623200693597380355420276946
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/19.flash_ctrl_disable/latest/run.log

  UVM_ERROR @ 18864.2 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 18864.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 4 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_serr_address_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 5 failures:
- Test flash_ctrl_serr_address has 5 failures.
  - 0.flash_ctrl_serr_address.80623182727165168636293906136313233276018210833327211164024621354930816239499
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_serr_address/latest/run.log
```
  UVM_FATAL @ 2159379.5 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_address_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000007a0
  UVM_INFO @ 2159379.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.flash_ctrl_serr_address.46344892768058871004199951023572887783024768279395574713080659409130891898012
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_serr_address/latest/run.log
```
  UVM_FATAL @ 229879.8 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_address_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000ea770
  UVM_INFO @ 229879.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_oversize_error_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 4 failures:

Test flash_ctrl_oversize_error has 4 failures.

0.flash_ctrl_oversize_error.7716652093087671496168076318159136815139737132289435978153619094571720466349
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_oversize_error/latest/run.log

  UVM_ERROR @ 9571.9 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_oversize_error_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 9571.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_oversize_error.42780001693687492090073851494787811992893561804557574738181976558202488633640
Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_oversize_error/latest/run.log

  UVM_ERROR @ 8010.4 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_oversize_error_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 8010.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_common_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 4 failures:

Test flash_ctrl_sec_cm has 4 failures.

0.flash_ctrl_sec_cm.31838329563225512455325249972405918128536010879168983110102546576262544582262
Line 321, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_sec_cm/latest/run.log

  UVM_ERROR @ 145644.1 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 145644.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_sec_cm.67684335605548944671027081178749502497812408008302976949283030744296832880271
Line 299, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_sec_cm/latest/run.log

  UVM_ERROR @ 42554.8 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 42554.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_serr_counter_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 4 failures:
- Test flash_ctrl_serr_counter has 4 failures.
  - 1.flash_ctrl_serr_counter.9512067174771565198391397242918240443168114980641132076773170826399160756522
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_serr_counter/latest/run.log
```
  UVM_FATAL @ 229658.2 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_counter_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00003750
  UVM_INFO @ 229658.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.flash_ctrl_serr_counter.96488783509587530877955899699710753874328280905955498736672522794290231073601
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/2.flash_ctrl_serr_counter/latest/run.log
```
  UVM_FATAL @ 108397.1 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_serr_counter_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000034b0
  UVM_INFO @ 108397.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_disable_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 4 failures:
- Test flash_ctrl_disable has 4 failures.
  - 7.flash_ctrl_disable.5101097968648477146547979583764135820950851012914987806018840534569456752917
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_disable/latest/run.log
```
  UVM_FATAL @ 19895.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000019a0
  UVM_INFO @ 19895.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 20.flash_ctrl_disable.51347518382847690169613750236857691967908070026558023969868969532377056768063
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/20.flash_ctrl_disable/latest/run.log
```
  UVM_FATAL @ 20536.0 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000cf0
  UVM_INFO @ 20536.0 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_derr_detect_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 3 failures:

Test flash_ctrl_derr_detect has 3 failures.

0.flash_ctrl_derr_detect.59212610374278896813767140541901633726431801238064603988066132466653472625007
Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest/run.log

  UVM_ERROR @ 18166.9 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_derr_detect_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 18166.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.flash_ctrl_derr_detect.24348846209738186790733780814930152745986098812391815079217034248243505146426
Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest/run.log

  UVM_ERROR @ 99874.5 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_derr_detect_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 99874.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_access_after_disable_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 3 failures:
- Test flash_ctrl_access_after_disable has 3 failures.
  - 0.flash_ctrl_access_after_disable.25343587632281770523344940437735487857109380449799703099062337498063596029321
    Line 292, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_access_after_disable/latest/run.log
```
  UVM_ERROR @ 10434.5 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_access_after_disable_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 10434.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.flash_ctrl_access_after_disable.76781788422055137933761558676534041847156303375231244437347102781342889013624
    Line 288, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/1.flash_ctrl_access_after_disable/latest/run.log
```
  UVM_ERROR @ 42570.5 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_access_after_disable_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 42570.5 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_derr_detect_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 2 failures:
- Test flash_ctrl_derr_detect has 2 failures.
  - 3.flash_ctrl_derr_detect.42016904472986183068535849184155327646879362932889656384697796630298279023814
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 39897.1 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_derr_detect_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 39897.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 4.flash_ctrl_derr_detect.20075613384165595822047044345323693060037975618692467622551757115616489579974
    Line 293, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest/run.log
```
  UVM_ERROR @ 86605.7 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_derr_detect_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 86605.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:403) [flash_ctrl_write_word_sweep_vseq] Check failed flash_op.otf_addr[*] == *'b* (* [*] vs * [*]) prog_flash gets unexpected address not * byte aligned has 1 failures:
- Test flash_ctrl_write_word_sweep has 1 failures.
  - 0.flash_ctrl_write_word_sweep.85885949324293325676681969962579595791654654632888580748558558233305835704534
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/0.flash_ctrl_write_word_sweep/latest/run.log
```
  UVM_ERROR @ 18795.4 ns: (flash_ctrl_otf_base_vseq.sv:403) [uvm_test_top.env.virtual_sequencer.flash_ctrl_write_word_sweep_vseq] Check failed flash_op.otf_addr[2] == 1'b0 (1 [0x1] vs 0 [0x0]) prog_flash gets unexpected address not 8 byte aligned
  UVM_INFO @ 18795.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_base_scoreboard.sv:241) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 1 failures:
- Test flash_ctrl_ro has 1 failures.
  - 3.flash_ctrl_ro.77147081454440404554423550735686681754944995016531575209214046670139136332523
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/3.flash_ctrl_ro/latest/run.log
```
  UVM_ERROR @ 205281.4 ns: (cip_base_scoreboard.sv:241) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 205281.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_oversize_error_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_oversize_error has 1 failures.
  - 4.flash_ctrl_oversize_error.78633110665220386250325267897418334286659236448277101807658359795306793538665
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_oversize_error/latest/run.log
```
  UVM_FATAL @ 18697.3 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_oversize_error_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00001f30
  UVM_INFO @ 18697.3 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_otf_base_vseq.sv:405) [flash_ctrl_common_vseq] Check failed (wd % * == *) prog_flash gets unexpected odd bus word count has 1 failures:
- Test flash_ctrl_sec_cm has 1 failures.
  - 4.flash_ctrl_sec_cm.41383565163371045177291777691105551885583953854112338465088401618925497700544
    Line 345, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_sec_cm/latest/run.log
```
  UVM_ERROR @ 39935.9 ns: (flash_ctrl_otf_base_vseq.sv:405) [uvm_test_top.env.virtual_sequencer.flash_ctrl_common_vseq] Check failed (wd % 2 == 0) prog_flash gets unexpected odd bus word count
  UVM_INFO @ 39935.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_filesystem_support_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_fs_sup has 1 failures.
  - 4.flash_ctrl_fs_sup.32099196271748346658613213000696991747006939154022284988871013223324230668371
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/4.flash_ctrl_fs_sup/latest/run.log
```
  UVM_FATAL @ 18646.8 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_filesystem_support_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x000009e8
  UVM_INFO @ 18646.8 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL (flash_ctrl_base_vseq.sv:81) [flash_ctrl_intr_wr_vseq] Check failed (!address_was_written(addr)) Overwriting address * has 1 failures:
- Test flash_ctrl_intr_wr_slow_flash has 1 failures.
  - 7.flash_ctrl_intr_wr_slow_flash.37184144452565429513107547549134816329703869605376530887271929723848975719772
    Line 282, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr_slow_flash/latest/run.log
```
  UVM_FATAL @ 118488.7 ns: (flash_ctrl_base_vseq.sv:81) [uvm_test_top.env.virtual_sequencer.flash_ctrl_intr_wr_vseq] Check failed (!address_was_written(addr)) Overwriting address 0x00000a10
  UVM_INFO @ 118488.7 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (flash_ctrl_disable_vseq.sv:32) [flash_ctrl_disable_vseq] Check failed cfg.tlul_core_obs_cnt == cfg.tlul_core_exp_cnt (* [*] vs * [*]) has 1 failures:
- Test flash_ctrl_disable has 1 failures.
  - 28.flash_ctrl_disable.92101771357184285385187113070210804847946974882459292094747917708624901391074
    Line 283, in log /container/opentitan-public/scratch/os_regression/flash_ctrl-sim-vcs/28.flash_ctrl_disable/latest/run.log
```
  UVM_ERROR @ 23680.9 ns: (flash_ctrl_disable_vseq.sv:32) [uvm_test_top.env.virtual_sequencer.flash_ctrl_disable_vseq] Check failed cfg.tlul_core_obs_cnt == cfg.tlul_core_exp_cnt (16 [0x10] vs 12 [0xc])
  UVM_INFO @ 23680.9 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```