FLASH_CTRL Simulation Results

Tuesday May 07 2024 19:02:25 UTC

GitHub Revision: 18c8953cf1

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 23463731882259624708557902606691160899163550314542713462365308032920382521803

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke flash_ctrl_smoke 4.424m 687.661us 50 50 100.00
V1 smoke_hw flash_ctrl_smoke_hw 26.390s 52.040us 5 5 100.00
V1 csr_hw_reset flash_ctrl_csr_hw_reset 46.690s 253.231us 5 5 100.00
V1 csr_rw flash_ctrl_csr_rw 17.680s 255.768us 20 20 100.00
V1 csr_bit_bash flash_ctrl_csr_bit_bash 1.725m 45.519ms 5 5 100.00
V1 csr_aliasing flash_ctrl_csr_aliasing 1.078m 1.801ms 5 5 100.00
V1 csr_mem_rw_with_rand_reset flash_ctrl_csr_mem_rw_with_rand_reset 19.990s 45.017us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr flash_ctrl_csr_rw 17.680s 255.768us 20 20 100.00
flash_ctrl_csr_aliasing 1.078m 1.801ms 5 5 100.00
V1 mem_walk flash_ctrl_mem_walk 13.540s 196.206us 5 5 100.00
V1 mem_partial_access flash_ctrl_mem_partial_access 14.060s 53.729us 5 5 100.00
V1 TOTAL 120 120 100.00
V2 sw_op flash_ctrl_sw_op 26.170s 25.244us 5 5 100.00
V2 host_read_direct flash_ctrl_host_dir_rd 2.143m 69.271us 5 5 100.00
V2 rma_hw_if flash_ctrl_hw_rma 32.565m 122.562ms 3 3 100.00
flash_ctrl_hw_rma_reset 17.053m 230.214ms 20 20 100.00
flash_ctrl_lcmgr_intg 13.790s 63.913us 20 20 100.00
V2 host_controller_arb flash_ctrl_host_ctrl_arb 41.138m 595.731ms 5 5 100.00
V2 erase_suspend flash_ctrl_erase_suspend 9.241m 15.954ms 5 5 100.00
V2 program_reset flash_ctrl_prog_reset 15.640s 32.300us 5 30 16.67
V2 full_memory_access flash_ctrl_full_mem_access 1.180h 97.825ms 5 5 100.00
V2 rd_buff_eviction flash_ctrl_rd_buff_evict 2.518m 703.482us 5 5 100.00
V2 rd_buff_eviction_w_ecc flash_ctrl_rw_evict 31.830s 59.152us 7 40 17.50
flash_ctrl_rw_evict_all_en 31.690s 143.252us 8 40 20.00
flash_ctrl_re_evict 40.150s 518.073us 20 20 100.00
V2 host_arb flash_ctrl_phy_arb 9.103m 2.790ms 20 20 100.00
V2 host_interleave flash_ctrl_phy_arb 9.103m 2.790ms 20 20 100.00
V2 memory_protection flash_ctrl_mp_regions 13.963m 33.470ms 20 20 100.00
V2 fetch_code flash_ctrl_fetch_code 27.000s 370.395us 10 10 100.00
V2 all_partitions flash_ctrl_rand_ops 25.037m 1.866ms 20 20 100.00
V2 error_mp flash_ctrl_error_mp 43.232m 80.527ms 10 10 100.00
V2 error_prog_win flash_ctrl_error_prog_win 17.479m 1.549ms 10 10 100.00
V2 error_prog_type flash_ctrl_error_prog_type 56.472m 4.512ms 5 5 100.00
V2 error_read_seed flash_ctrl_hw_read_seed_err 14.160s 106.312us 20 20 100.00
V2 read_write_overflow flash_ctrl_oversize_error 28.790s 38.853us 0 5 0.00
V2 flash_ctrl_disable flash_ctrl_disable 22.320s 6.581us 31 50 62.00
V2 flash_ctrl_connect flash_ctrl_connect 16.020s 25.748us 80 80 100.00
V2 stress_all flash_ctrl_stress_all 25.770m 1.556ms 5 5 100.00
V2 secret_partition flash_ctrl_hw_sec_otp 4.300m 22.953ms 50 50 100.00
flash_ctrl_otp_reset 2.236m 92.643us 80 80 100.00
V2 isolation_partition flash_ctrl_hw_rma 32.565m 122.562ms 3 3 100.00
V2 interrupts flash_ctrl_intr_rd 4.270m 4.673ms 40 40 100.00
flash_ctrl_intr_wr 16.480s 161.689us 0 10 0.00
flash_ctrl_intr_rd_slow_flash 5.866m 36.467ms 40 40 100.00
flash_ctrl_intr_wr_slow_flash 17.790s 3.166ms 0 10 0.00
V2 invalid_op flash_ctrl_invalid_op 1.667m 34.406ms 20 20 100.00
V2 mid_op_rst flash_ctrl_mid_op_rst 1.219m 4.009ms 5 5 100.00
V2 double_bit_err flash_ctrl_read_word_sweep_derr 22.620s 62.240us 5 5 100.00
flash_ctrl_ro_derr 3.038m 3.564ms 10 10 100.00
flash_ctrl_rw_derr 3.729m 959.161us 0 10 0.00
flash_ctrl_derr_detect 43.240s 39.897us 0 5 0.00
flash_ctrl_integrity 2.152m 521.772us 0 5 0.00
V2 single_bit_err flash_ctrl_read_word_sweep_serr 22.870s 366.496us 5 5 100.00
flash_ctrl_ro_serr 2.817m 673.725us 10 10 100.00
flash_ctrl_rw_serr 4.783m 7.882ms 0 10 0.00
V2 singlebit_err_counter flash_ctrl_serr_counter 1.453m 2.833ms 1 5 20.00
V2 singlebit_err_address flash_ctrl_serr_address 1.150m 2.159ms 0 5 0.00
V2 scramble flash_ctrl_wo 4.766m 5.642ms 20 20 100.00
flash_ctrl_write_word_sweep 13.210s 18.795us 0 1 0.00
flash_ctrl_read_word_sweep 13.140s 54.751us 1 1 100.00
flash_ctrl_ro 2.667m 1.377ms 19 20 95.00
flash_ctrl_rw 12.670m 8.977ms 20 20 100.00
V2 filesystem_support flash_ctrl_fs_sup 36.410s 789.151us 4 5 80.00
V2 rma_write_process_error flash_ctrl_rma_err 19.125m 73.794ms 3 3 100.00
flash_ctrl_hw_prog_rma_wipe_err 2.868m 10.020ms 20 20 100.00
V2 alert_test flash_ctrl_alert_test 14.350s 172.227us 50 50 100.00
V2 intr_test flash_ctrl_intr_test 14.830s 27.682us 50 50 100.00
V2 tl_d_oob_addr_access flash_ctrl_tl_errors 20.320s 642.701us 20 20 100.00
V2 tl_d_illegal_access flash_ctrl_tl_errors 20.320s 642.701us 20 20 100.00
V2 tl_d_outstanding_access flash_ctrl_csr_hw_reset 46.690s 253.231us 5 5 100.00
flash_ctrl_csr_rw 17.680s 255.768us 20 20 100.00
flash_ctrl_csr_aliasing 1.078m 1.801ms 5 5 100.00
flash_ctrl_same_csr_outstanding 35.460s 220.321us 20 20 100.00
V2 tl_d_partial_access flash_ctrl_csr_hw_reset 46.690s 253.231us 5 5 100.00
flash_ctrl_csr_rw 17.680s 255.768us 20 20 100.00
flash_ctrl_csr_aliasing 1.078m 1.801ms 5 5 100.00
flash_ctrl_same_csr_outstanding 35.460s 220.321us 20 20 100.00
V2 TOTAL 837 1013 82.63
V2S shadow_reg_update_error flash_ctrl_shadow_reg_errors 16.350s 14.653us 20 20 100.00
V2S shadow_reg_read_clear_staged_value flash_ctrl_shadow_reg_errors 16.350s 14.653us 20 20 100.00
V2S shadow_reg_storage_error flash_ctrl_shadow_reg_errors 16.350s 14.653us 20 20 100.00
V2S shadowed_reset_glitch flash_ctrl_shadow_reg_errors 16.350s 14.653us 20 20 100.00
V2S shadow_reg_update_error_with_csr_rw flash_ctrl_shadow_reg_errors_with_csr_rw 16.270s 12.411us 20 20 100.00
V2S tl_intg_err flash_ctrl_sec_cm 43.680s 39.936us 0 5 0.00
flash_ctrl_tl_intg_err 15.243m 910.930us 20 20 100.00
V2S sec_cm_reg_bus_integrity flash_ctrl_tl_intg_err 15.243m 910.930us 20 20 100.00
V2S sec_cm_host_bus_integrity flash_ctrl_tl_intg_err 15.243m 910.930us 20 20 100.00
V2S sec_cm_mem_bus_integrity flash_ctrl_rd_intg 32.610s 543.039us 3 3 100.00
flash_ctrl_wr_intg 14.880s 157.250us 3 3 100.00
V2S sec_cm_scramble_key_sideload flash_ctrl_smoke 4.424m 687.661us 50 50 100.00
V2S sec_cm_lc_ctrl_intersig_mubi flash_ctrl_otp_reset 2.236m 92.643us 80 80 100.00
flash_ctrl_disable 22.320s 6.581us 31 50 62.00
flash_ctrl_sec_info_access 1.460m 3.467ms 50 50 100.00
flash_ctrl_connect 16.020s 25.748us 80 80 100.00
V2S sec_cm_ctrl_config_regwen flash_ctrl_config_regwen 14.260s 38.795us 5 5 100.00
V2S sec_cm_data_regions_config_regwen flash_ctrl_csr_rw 17.680s 255.768us 20 20 100.00
V2S sec_cm_data_regions_config_shadow flash_ctrl_shadow_reg_errors 16.350s 14.653us 20 20 100.00
V2S sec_cm_info_regions_config_regwen flash_ctrl_csr_rw 17.680s 255.768us 20 20 100.00
V2S sec_cm_info_regions_config_shadow flash_ctrl_shadow_reg_errors 16.350s 14.653us 20 20 100.00
V2S sec_cm_bank_config_regwen flash_ctrl_csr_rw 17.680s 255.768us 20 20 100.00
V2S sec_cm_bank_config_shadow flash_ctrl_shadow_reg_errors 16.350s 14.653us 20 20 100.00
V2S sec_cm_mem_ctrl_global_esc flash_ctrl_disable 22.320s 6.581us 31 50 62.00
V2S sec_cm_mem_ctrl_local_esc flash_ctrl_rd_intg 32.610s 543.039us 3 3 100.00
flash_ctrl_access_after_disable 13.660s 42.571us 0 3 0.00
V2S sec_cm_mem_disable_config_mubi flash_ctrl_disable 22.320s 6.581us 31 50 62.00
V2S sec_cm_exec_config_redun flash_ctrl_fetch_code 27.000s 370.395us 10 10 100.00
V2S sec_cm_mem_scramble flash_ctrl_rw 12.670m 8.977ms 20 20 100.00
V2S sec_cm_mem_integrity flash_ctrl_rw_serr 4.783m 7.882ms 0 10 0.00
flash_ctrl_rw_derr 3.729m 959.161us 0 10 0.00
flash_ctrl_integrity 2.152m 521.772us 0 5 0.00
V2S sec_cm_rma_entry_mem_sec_wipe flash_ctrl_hw_rma 32.565m 122.562ms 3 3 100.00
V2S sec_cm_ctrl_fsm_sparse flash_ctrl_sec_cm 43.680s 39.936us 0 5 0.00
V2S sec_cm_phy_fsm_sparse flash_ctrl_sec_cm 43.680s 39.936us 0 5 0.00
V2S sec_cm_phy_prog_fsm_sparse flash_ctrl_sec_cm 43.680s 39.936us 0 5 0.00
V2S sec_cm_ctr_redun flash_ctrl_sec_cm 43.680s 39.936us 0 5 0.00
V2S sec_cm_phy_arbiter_ctrl_redun flash_ctrl_phy_arb_redun 25.660s 756.044us 5 5 100.00
V2S sec_cm_phy_host_grant_ctrl_consistency flash_ctrl_phy_host_grant_err 14.130s 53.094us 5 5 100.00
V2S sec_cm_phy_ack_ctrl_consistency flash_ctrl_phy_ack_consistency 14.420s 15.609us 5 5 100.00
V2S sec_cm_fifo_ctr_redun flash_ctrl_sec_cm 43.680s 39.936us 0 5 0.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse flash_ctrl_sec_cm 43.680s 39.936us 0 5 0.00
V2S sec_cm_prog_tl_lc_gate_fsm_sparse flash_ctrl_sec_cm 43.680s 39.936us 0 5 0.00
V2S TOTAL 136 144 94.44
V3 asymmetric_read_path flash_ctrl_rd_ooo 48.060s 339.845us 1 1 100.00
V3 stress_all_with_rand_reset flash_ctrl_stress_all_with_rand_reset 0 0 --
V3 TOTAL 1 1 100.00
TOTAL 1094 1278 85.60

Testplan Progress

Items Total Written Passing Progress
V1 9 9 9 100.00
V2 55 55 39 70.91
V2S 12 12 10 83.33
V3 2 1 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
94.90 95.81 93.39 94.81 89.80 98.03 94.61 97.87

Failure Buckets

Past Results