GPIO Simulation Results

Tuesday May 23 2023 07:02:27 UTC

GitHub Revision: `83db9403d`

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 1254715506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.660s	102.262us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.540s	141.197us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.670s	48.145us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.670s	25.024us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.140s	314.637us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.920s	57.670us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.560s	63.943us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.670s	25.024us	20	20	100.00
		gpio_csr_aliasing	0.920s	57.670us	5	5	100.00
V1		TOTAL			155	155	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.410s	149.107us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.460s	37.588us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.960s	42.187us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.570s	205.670us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.540s	120.575us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	4.140s	353.829us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.820s	2.030ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.450s	1.317ms	50	50	100.00
V2	full_random	gpio_full_random	1.270s	76.500us	50	50	100.00
V2	stress_all	gpio_stress_all	4.982m	18.430ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.630s	14.270us	50	50	100.00
V2	intr_test	gpio_intr_test	0.640s	31.531us	26	50	52.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.130s	146.162us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.130s	146.162us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.670s	25.024us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	131.189us	20	20	100.00
		gpio_csr_aliasing	0.920s	57.670us	5	5	100.00
		gpio_csr_hw_reset	0.670s	48.145us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.670s	25.024us	20	20	100.00
		gpio_same_csr_outstanding	0.880s	131.189us	20	20	100.00
		gpio_csr_aliasing	0.920s	57.670us	5	5	100.00
		gpio_csr_hw_reset	0.670s	48.145us	5	5	100.00
V2		TOTAL			616	640	96.25
V2S	tl_intg_err	gpio_tl_intg_err	1.520s	106.408us	20	20	100.00
		gpio_sec_cm	1.010s	477.205us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.520s	106.408us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	41.822m	448.258ms	50	50	100.00
V3		TOTAL			50	50	100.00
		TOTAL			846	870	97.24

Testplan Progress

Items	Total	Written	Passing	Progress
V1	7	7	7	100.00
V2	14	14	13	92.86
V2S	2	2	2	100.00
V3	1	1	1	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.61	99.07	99.10	100.00	--	99.80	99.68	100.00

Failure Buckets

UVM_ERROR (cip_base_vseq.sv:455) [gpio_common_vseq] Check failed exp_val == act_val (* [*] vs * [*]) when reading the intr CSRgpio_reg_block.intr_state

has 24 failures:

Test gpio_intr_test has 24 failures.

2.gpio_intr_test.2720959451
Line 220, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_intr_test/latest/run.log

  UVM_ERROR @   1379519 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 2115912031 [0x7e1e415f]) when reading the intr CSRgpio_reg_block.intr_state
  UVM_INFO @   1379519 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

3.gpio_intr_test.3476164604
Line 218, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/3.gpio_intr_test/latest/run.log

  UVM_ERROR @   3531895 ps: (cip_base_vseq.sv:455) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed exp_val == act_val (1 [0x1] vs 469303895 [0x1bf90257]) when reading the intr CSRgpio_reg_block.intr_state
  UVM_INFO @   3531895 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 22 more failures.