042415198f| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | gpio_smoke | 1.400s | 64.418us | 50 | 50 | 100.00 |
| gpio_smoke_no_pullup_pulldown | 1.550s | 180.551us | 50 | 50 | 100.00 | ||
| gpio_smoke_en_cdc_prim | 1.430s | 297.782us | 45 | 50 | 90.00 | ||
| gpio_smoke_no_pullup_pulldown_en_cdc_prim | 1.390s | 957.014us | 44 | 50 | 88.00 | ||
| V1 | csr_hw_reset | gpio_csr_hw_reset | 0.630s | 30.438us | 4 | 5 | 80.00 |
| V1 | csr_rw | gpio_csr_rw | 0.640s | 12.567us | 17 | 20 | 85.00 |
| V1 | csr_bit_bash | gpio_csr_bit_bash | 2.350s | 769.172us | 4 | 5 | 80.00 |
| V1 | csr_aliasing | gpio_csr_aliasing | 0.860s | 150.558us | 3 | 5 | 60.00 |
| V1 | csr_mem_rw_with_rand_reset | gpio_csr_mem_rw_with_rand_reset | 1.580s | 30.298us | 13 | 20 | 65.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | gpio_csr_rw | 0.640s | 12.567us | 17 | 20 | 85.00 |
| gpio_csr_aliasing | 0.860s | 150.558us | 3 | 5 | 60.00 | ||
| V1 | TOTAL | 230 | 255 | 90.20 | |||
| V2 | direct_and_masked_out | gpio_random_dout_din | 1.370s | 1.002ms | 50 | 50 | 100.00 |
| gpio_random_dout_din_no_pullup_pulldown | 1.410s | 59.949us | 50 | 50 | 100.00 | ||
| V2 | out_in_regs_read_write | gpio_dout_din_regs_random_rw | 0.950s | 406.026us | 50 | 50 | 100.00 |
| V2 | gpio_interrupt_programming | gpio_intr_rand_pgm | 1.430s | 240.196us | 50 | 50 | 100.00 |
| V2 | random_interrupt_trigger | gpio_rand_intr_trigger | 3.680s | 488.326us | 50 | 50 | 100.00 |
| V2 | interrupt_and_noise_filter | gpio_intr_with_filter_rand_intr_event | 3.880s | 383.249us | 50 | 50 | 100.00 |
| V2 | noise_filter_stress | gpio_filter_stress | 29.090s | 4.980ms | 50 | 50 | 100.00 |
| V2 | regs_long_reads_and_writes | gpio_random_long_reg_writes_reg_reads | 6.390s | 2.260ms | 50 | 50 | 100.00 |
| V2 | full_random | gpio_full_random | 1.120s | 89.304us | 50 | 50 | 100.00 |
| V2 | stress_all | gpio_stress_all | 3.823m | 30.634ms | 50 | 50 | 100.00 |
| V2 | alert_test | gpio_alert_test | 0.640s | 33.105us | 50 | 50 | 100.00 |
| V2 | intr_test | gpio_intr_test | 0.660s | 95.574us | 39 | 50 | 78.00 |
| V2 | tl_d_oob_addr_access | gpio_tl_errors | 3.040s | 652.085us | 17 | 20 | 85.00 |
| V2 | tl_d_illegal_access | gpio_tl_errors | 3.040s | 652.085us | 17 | 20 | 85.00 |
| V2 | tl_d_outstanding_access | gpio_csr_rw | 0.640s | 12.567us | 17 | 20 | 85.00 |
| gpio_same_csr_outstanding | 0.870s | 62.409us | 19 | 20 | 95.00 | ||
| gpio_csr_aliasing | 0.860s | 150.558us | 3 | 5 | 60.00 | ||
| gpio_csr_hw_reset | 0.630s | 30.438us | 4 | 5 | 80.00 | ||
| V2 | tl_d_partial_access | gpio_csr_rw | 0.640s | 12.567us | 17 | 20 | 85.00 |
| gpio_same_csr_outstanding | 0.870s | 62.409us | 19 | 20 | 95.00 | ||
| gpio_csr_aliasing | 0.860s | 150.558us | 3 | 5 | 60.00 | ||
| gpio_csr_hw_reset | 0.630s | 30.438us | 4 | 5 | 80.00 | ||
| V2 | TOTAL | 625 | 640 | 97.66 | |||
| V2S | tl_intg_err | gpio_tl_intg_err | 1.460s | 140.663us | 18 | 20 | 90.00 |
| gpio_sec_cm | 0.960s | 330.159us | 5 | 5 | 100.00 | ||
| V2S | sec_cm_bus_integrity | gpio_tl_intg_err | 1.460s | 140.663us | 18 | 20 | 90.00 |
| V2S | TOTAL | 23 | 25 | 92.00 | |||
| V3 | stress_all_with_rand_reset | gpio_stress_all_with_rand_reset | 42.125m | 531.478ms | 50 | 50 | 100.00 |
| V3 | TOTAL | 50 | 50 | 100.00 | |||
| TOTAL | 928 | 970 | 95.67 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 2 | 22.22 |
| V2 | 14 | 14 | 11 | 78.57 |
| V2S | 2 | 2 | 1 | 50.00 |
| V3 | 1 | 1 | 1 | 100.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 99.61 | 99.06 | 99.10 | 100.00 | -- | 99.80 | 99.68 | 100.00 |
Exit reason: Error: User command failed Job returned non-zero exit code has 42 failures:
Test gpio_csr_aliasing has 2 failures.
0.gpio_csr_aliasing.85081379396848915418091401583018274228206653798481226287453349805352956960138
Log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_csr_aliasing/latest/run.log
[make]: simulate
cd /workspace/0.gpio_csr_aliasing/latest && /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470499210 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.gpio_csr_aliasing.3470499210
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:49 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
1.gpio_csr_aliasing.20038936530143645610350021582265792332577894886018286940153913249038078864930
Log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_csr_aliasing/latest/run.log
[make]: simulate
cd /workspace/1.gpio_csr_aliasing/latest && /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255253026 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_aliasing.2255253026
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:49 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test gpio_csr_mem_rw_with_rand_reset has 7 failures.
1.gpio_csr_mem_rw_with_rand_reset.38717951803861812318749595139941723372216517041351355752264558176418606702522
Log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_csr_mem_rw_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/1.gpio_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19750842 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_mem_rw_with_rand_reset.19750842
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:50 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
2.gpio_csr_mem_rw_with_rand_reset.68334858011596968076041425707179802862322828579422481483023503959131205526503
Log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_csr_mem_rw_with_rand_reset/latest/run.log
[make]: simulate
cd /workspace/2.gpio_csr_mem_rw_with_rand_reset/latest && /workspace/cover_reg_top/simv +do_clear_all_interrupts=0 +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813191143 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.gpio_csr_mem_rw_with_rand_reset.2813191143
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:50 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 5 more failures.
Test gpio_csr_bit_bash has 1 failures.
1.gpio_csr_bit_bash.6459177090972513419741138518542164711521833394423778741956395865435096183519
Log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_csr_bit_bash/latest/run.log
[make]: simulate
cd /workspace/1.gpio_csr_bit_bash/latest && /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924704479 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.gpio_csr_bit_bash.2924704479
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:49 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
Test gpio_intr_test has 11 failures.
3.gpio_intr_test.100312706132736226555237058121329941424245010038625672203701053598571339016787
Log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/3.gpio_intr_test/latest/run.log
[make]: simulate
cd /workspace/3.gpio_intr_test/latest && /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255500371 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.gpio_intr_test.1255500371
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:49 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
4.gpio_intr_test.98287308931367637685802150558724955870986024880919380932351379137631588513247
Log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/4.gpio_intr_test/latest/run.log
[make]: simulate
cd /workspace/4.gpio_intr_test/latest && /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691495391 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_intr_test.2691495391
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:50 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 9 more failures.
Test gpio_csr_hw_reset has 1 failures.
4.gpio_csr_hw_reset.104532822518433697140781570934647006888002209158727312511101903946257438120356
Log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/4.gpio_csr_hw_reset/latest/run.log
[make]: simulate
cd /workspace/4.gpio_csr_hw_reset/latest && /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000881060 -assert nopostproc +UVM_TESTNAME=gpio_base_test +UVM_TEST_SEQ=gpio_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.gpio_csr_hw_reset.4000881060
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Jan 7 12:50 2024
Cannot find license file.
Make sure that you have a license file and that your
LM_LICENSE_FILE is pointing to the right location.
make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:175: simulate] Error 255
... and 6 more tests.