GPIO Simulation Results

Wednesday January 10 2024 20:03:22 UTC

GitHub Revision: cf38c1d296

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 55803132295021657086212552594002090640066687299415498461130788370399872772386

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke gpio_smoke 1.420s 56.730us 48 50 96.00
gpio_smoke_no_pullup_pulldown 1.430s 1.270ms 47 50 94.00
gpio_smoke_en_cdc_prim 1.520s 98.003us 50 50 100.00
gpio_smoke_no_pullup_pulldown_en_cdc_prim 1.500s 344.511us 50 50 100.00
V1 csr_hw_reset gpio_csr_hw_reset 0.650s 37.363us 5 5 100.00
V1 csr_rw gpio_csr_rw 0.640s 33.491us 20 20 100.00
V1 csr_bit_bash gpio_csr_bit_bash 3.420s 525.461us 5 5 100.00
V1 csr_aliasing gpio_csr_aliasing 0.840s 34.828us 5 5 100.00
V1 csr_mem_rw_with_rand_reset gpio_csr_mem_rw_with_rand_reset 1.580s 32.914us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr gpio_csr_rw 0.640s 33.491us 20 20 100.00
gpio_csr_aliasing 0.840s 34.828us 5 5 100.00
V1 TOTAL 250 255 98.04
V2 direct_and_masked_out gpio_random_dout_din 1.300s 55.258us 49 50 98.00
gpio_random_dout_din_no_pullup_pulldown 1.340s 119.051us 49 50 98.00
V2 out_in_regs_read_write gpio_dout_din_regs_random_rw 1.020s 52.131us 48 50 96.00
V2 gpio_interrupt_programming gpio_intr_rand_pgm 1.510s 97.167us 49 50 98.00
V2 random_interrupt_trigger gpio_rand_intr_trigger 3.580s 2.336ms 49 50 98.00
V2 interrupt_and_noise_filter gpio_intr_with_filter_rand_intr_event 3.730s 92.468us 50 50 100.00
V2 noise_filter_stress gpio_filter_stress 31.480s 892.603us 50 50 100.00
V2 regs_long_reads_and_writes gpio_random_long_reg_writes_reg_reads 6.700s 3.064ms 50 50 100.00
V2 full_random gpio_full_random 1.070s 173.778us 49 50 98.00
V2 stress_all gpio_stress_all 4.078m 278.852ms 50 50 100.00
V2 alert_test gpio_alert_test 0.630s 20.597us 49 50 98.00
V2 intr_test gpio_intr_test 0.680s 14.336us 50 50 100.00
V2 tl_d_oob_addr_access gpio_tl_errors 3.250s 740.420us 20 20 100.00
V2 tl_d_illegal_access gpio_tl_errors 3.250s 740.420us 20 20 100.00
V2 tl_d_outstanding_access gpio_csr_rw 0.640s 33.491us 20 20 100.00
gpio_same_csr_outstanding 0.900s 326.788us 20 20 100.00
gpio_csr_aliasing 0.840s 34.828us 5 5 100.00
gpio_csr_hw_reset 0.650s 37.363us 5 5 100.00
V2 tl_d_partial_access gpio_csr_rw 0.640s 33.491us 20 20 100.00
gpio_same_csr_outstanding 0.900s 326.788us 20 20 100.00
gpio_csr_aliasing 0.840s 34.828us 5 5 100.00
gpio_csr_hw_reset 0.650s 37.363us 5 5 100.00
V2 TOTAL 632 640 98.75
V2S tl_intg_err gpio_tl_intg_err 1.480s 418.062us 20 20 100.00
gpio_sec_cm 0.930s 98.269us 5 5 100.00
V2S sec_cm_bus_integrity gpio_tl_intg_err 1.480s 418.062us 20 20 100.00
V2S TOTAL 25 25 100.00
V3 stress_all_with_rand_reset gpio_stress_all_with_rand_reset 43.842m 876.531ms 50 50 100.00
V3 TOTAL 50 50 100.00
TOTAL 957 970 98.66

Testplan Progress

Items Total Written Passing Progress
V1 9 9 7 77.78
V2 14 14 7 50.00
V2S 2 2 2 100.00
V3 1 1 1 100.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
99.61 99.06 99.10 100.00 -- 99.80 99.68 100.00

Failure Buckets

Past Results