GPIO Simulation Results

Tuesday March 05 2024 20:02:48 UTC

GitHub Revision: c30684b3ca

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 61875946985821051720030118255902427822651914203242934898647746371735217685454

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.560s	108.580us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.530s	264.848us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.500s	103.247us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.470s	54.677us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.650s	34.133us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.660s	40.277us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.330s	325.903us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.860s	34.127us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.480s	30.217us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.660s	40.277us	20	20	100.00
		gpio_csr_aliasing	0.860s	34.127us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.350s	72.413us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.440s	288.756us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.960s	81.884us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.530s	90.486us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.550s	129.843us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	4.010s	96.662us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.530s	4.186ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	5.990s	265.595us	50	50	100.00
V2	full_random	gpio_full_random	1.120s	373.124us	50	50	100.00
V2	stress_all	gpio_stress_all	4.014m	20.017ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.670s	14.433us	50	50	100.00
V2	intr_test	gpio_intr_test	0.660s	37.274us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.870s	581.360us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.870s	581.360us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.660s	40.277us	20	20	100.00
		gpio_same_csr_outstanding	0.900s	46.031us	20	20	100.00
		gpio_csr_aliasing	0.860s	34.127us	5	5	100.00
		gpio_csr_hw_reset	0.650s	34.133us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.660s	40.277us	20	20	100.00
		gpio_same_csr_outstanding	0.900s	46.031us	20	20	100.00
		gpio_csr_aliasing	0.860s	34.127us	5	5	100.00
		gpio_csr_hw_reset	0.650s	34.133us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.540s	1.026ms	20	20	100.00
		gpio_sec_cm	0.940s	89.496us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.540s	1.026ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	41.307m	221.100ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			934	970	96.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:827) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 36 failures:
  • Test gpio_stress_all_with_rand_reset has 36 failures.

    • 0.gpio_stress_all_with_rand_reset.110641636139062395081037286997866244334958646620026161829914709938571415493350
      Line 2114, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 28957380982 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 28957380982 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.gpio_stress_all_with_rand_reset.51572293442238767458259994120317008919243685717255562523544532174741422002316
      Line 2916, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 73837210752 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 73837210752 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 34 more failures.

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