GPIO Simulation Results

Thursday March 07 2024 20:02:34 UTC

GitHub Revision: 36c168c253

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 132539995404104259171688804297348475616986265371189902218943342622053800053

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.550s	67.023us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.470s	620.152us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.490s	345.722us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.490s	153.255us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.670s	79.083us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.650s	43.792us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.850s	162.844us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.920s	77.442us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.820s	39.719us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.650s	43.792us	20	20	100.00
		gpio_csr_aliasing	0.920s	77.442us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.410s	61.528us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.420s	83.600us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.020s	163.810us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.570s	89.969us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.630s	252.126us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.950s	313.863us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	30.130s	1.005ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	7.080s	419.424us	50	50	100.00
V2	full_random	gpio_full_random	1.150s	251.485us	50	50	100.00
V2	stress_all	gpio_stress_all	3.994m	16.948ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.650s	37.427us	50	50	100.00
V2	intr_test	gpio_intr_test	0.660s	37.401us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.920s	151.018us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.920s	151.018us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.650s	43.792us	20	20	100.00
		gpio_same_csr_outstanding	0.900s	18.284us	20	20	100.00
		gpio_csr_aliasing	0.920s	77.442us	5	5	100.00
		gpio_csr_hw_reset	0.670s	79.083us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.650s	43.792us	20	20	100.00
		gpio_same_csr_outstanding	0.900s	18.284us	20	20	100.00
		gpio_csr_aliasing	0.920s	77.442us	5	5	100.00
		gpio_csr_hw_reset	0.670s	79.083us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.480s	118.789us	20	20	100.00
		gpio_sec_cm	1.030s	153.117us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.480s	118.789us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	50.976m	154.754ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			946	970	97.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:827) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
  • Test gpio_stress_all_with_rand_reset has 24 failures.

    • 1.gpio_stress_all_with_rand_reset.81592535767203769284568875303754877450787306581583332965946068054286177451119
      Line 6710, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 28946510484 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 28946510484 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.gpio_stress_all_with_rand_reset.115633937056454131705359670868898046369440045016789338851546832138704470064949
      Line 376, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1417165559 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1417165559 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

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