GPIO Simulation Results

Sunday March 10 2024 19:02:34 UTC

GitHub Revision: 8d1fda3660

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 55344925760588090643748974780216117977546302496149780891974223483299136808506

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.530s	139.680us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.670s	87.455us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.510s	1.423ms	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.660s	940.077us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.710s	16.437us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.700s	13.268us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.200s	4.106ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.890s	36.698us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.780s	47.482us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.700s	13.268us	20	20	100.00
		gpio_csr_aliasing	0.890s	36.698us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.550s	228.908us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.530s	59.545us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.060s	41.110us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.690s	51.109us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	4.630s	208.171us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	4.150s	114.637us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	31.690s	846.137us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.930s	2.215ms	50	50	100.00
V2	full_random	gpio_full_random	1.250s	140.658us	50	50	100.00
V2	stress_all	gpio_stress_all	4.817m	70.387ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.670s	43.160us	50	50	100.00
V2	intr_test	gpio_intr_test	0.680s	19.711us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.710s	190.398us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.710s	190.398us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.700s	13.268us	20	20	100.00
		gpio_same_csr_outstanding	1.100s	211.906us	20	20	100.00
		gpio_csr_aliasing	0.890s	36.698us	5	5	100.00
		gpio_csr_hw_reset	0.710s	16.437us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.700s	13.268us	20	20	100.00
		gpio_same_csr_outstanding	1.100s	211.906us	20	20	100.00
		gpio_csr_aliasing	0.890s	36.698us	5	5	100.00
		gpio_csr_hw_reset	0.710s	16.437us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.720s	1.321ms	20	20	100.00
		gpio_sec_cm	1.040s	175.508us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.720s	1.321ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	48.558m	1.180s	27	50	54.00
V3		TOTAL			27	50	54.00
		TOTAL			947	970	97.63

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:827) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 23 failures:
  • Test gpio_stress_all_with_rand_reset has 23 failures.

    • 0.gpio_stress_all_with_rand_reset.29880456732898736344940822919856144189322398440614922442140345163649873791932
      Line 3419, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 42884156170 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 42884156170 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.gpio_stress_all_with_rand_reset.96228158432604252915887667797898463831887344396454534785300333696257296943045
      Line 1950, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6825600438 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6825600438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 21 more failures.

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