GPIO Simulation Results

Tuesday March 12 2024 19:02:37 UTC

GitHub Revision: bc285b7382

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 8078106501385188224785993882809517173695187907049792415947230968390919037084

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.510s	408.513us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.440s	87.773us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.590s	155.716us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.400s	175.840us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.670s	19.805us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.660s	15.219us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.320s	252.959us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.910s	63.162us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	2.030s	345.849us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.660s	15.219us	20	20	100.00
		gpio_csr_aliasing	0.910s	63.162us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.230s	481.575us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.380s	153.581us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.950s	30.645us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.480s	576.521us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.510s	121.212us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.690s	302.325us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.000s	1.601ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.200s	444.961us	50	50	100.00
V2	full_random	gpio_full_random	1.150s	108.255us	50	50	100.00
V2	stress_all	gpio_stress_all	3.846m	241.217ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.640s	22.069us	50	50	100.00
V2	intr_test	gpio_intr_test	0.690s	16.288us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.420s	201.558us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.420s	201.558us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.660s	15.219us	20	20	100.00
		gpio_same_csr_outstanding	0.930s	31.597us	20	20	100.00
		gpio_csr_aliasing	0.910s	63.162us	5	5	100.00
		gpio_csr_hw_reset	0.670s	19.805us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.660s	15.219us	20	20	100.00
		gpio_same_csr_outstanding	0.930s	31.597us	20	20	100.00
		gpio_csr_aliasing	0.910s	63.162us	5	5	100.00
		gpio_csr_hw_reset	0.670s	19.805us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.460s	460.760us	20	20	100.00
		gpio_sec_cm	0.970s	444.507us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.460s	460.760us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	36.377m	81.331ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			941	970	97.01

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:827) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 29 failures:
  • Test gpio_stress_all_with_rand_reset has 29 failures.

    • 1.gpio_stress_all_with_rand_reset.66792464258499719827203133577363841707771968227293942889738169509422092673755
      Line 5498, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 18916403329 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 18916403329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.gpio_stress_all_with_rand_reset.48783590569080280325281440149580737026273708174820975943095164891639099836309
      Line 2843, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 144976411001 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 144976411001 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 27 more failures.

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