GPIO Simulation Results

Thursday March 14 2024 19:02:18 UTC

GitHub Revision: e844018f2c

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 83239673812975098462159483702727474484560953854893181354811398969250076096082

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.520s	123.694us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.500s	499.670us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.590s	92.250us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.500s	307.897us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.680s	129.425us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.640s	108.009us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.500s	219.586us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.910s	139.027us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.680s	101.923us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.640s	108.009us	20	20	100.00
		gpio_csr_aliasing	0.910s	139.027us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.350s	286.572us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.440s	143.048us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.060s	26.894us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.560s	92.237us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.810s	248.853us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.860s	178.297us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.100s	3.157ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.440s	1.923ms	50	50	100.00
V2	full_random	gpio_full_random	1.110s	281.747us	50	50	100.00
V2	stress_all	gpio_stress_all	4.090m	86.734ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.650s	38.328us	50	50	100.00
V2	intr_test	gpio_intr_test	0.720s	44.732us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.560s	58.623us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.560s	58.623us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.640s	108.009us	20	20	100.00
		gpio_same_csr_outstanding	0.890s	162.287us	20	20	100.00
		gpio_csr_aliasing	0.910s	139.027us	5	5	100.00
		gpio_csr_hw_reset	0.680s	129.425us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.640s	108.009us	20	20	100.00
		gpio_same_csr_outstanding	0.890s	162.287us	20	20	100.00
		gpio_csr_aliasing	0.910s	139.027us	5	5	100.00
		gpio_csr_hw_reset	0.680s	129.425us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.520s	120.415us	20	20	100.00
		gpio_sec_cm	0.940s	83.352us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.520s	120.415us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	37.740m	330.908ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			942	970	97.11

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:827) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
  • Test gpio_stress_all_with_rand_reset has 28 failures.

    • 2.gpio_stress_all_with_rand_reset.93780910422629191108084258084966833981402411857094224816177911550900719314100
      Line 6952, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 48203461567 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 48203461567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.gpio_stress_all_with_rand_reset.96654286792477304168371622580301632626757009034100803829619932835706985812439
      Line 10500, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/3.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 324866466158 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10014 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 324866466158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 26 more failures.

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