GPIO Simulation Results

Sunday March 17 2024 19:02:52 UTC

GitHub Revision: c187a82ee8

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 28440605375541353837496064678278045899395893237469128852560697715229879921060

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.520s	91.610us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.490s	359.592us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.550s	111.149us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.500s	376.650us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.700s	22.403us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.660s	46.655us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.480s	994.357us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.900s	31.914us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.560s	33.714us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.660s	46.655us	20	20	100.00
		gpio_csr_aliasing	0.900s	31.914us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.530s	112.954us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.400s	82.546us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.010s	86.265us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.600s	342.652us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.960s	560.885us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	4.040s	360.777us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	26.710s	12.437ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.920s	3.357ms	50	50	100.00
V2	full_random	gpio_full_random	1.180s	97.426us	50	50	100.00
V2	stress_all	gpio_stress_all	3.531m	29.838ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.640s	60.136us	50	50	100.00
V2	intr_test	gpio_intr_test	0.670s	30.272us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.490s	1.020ms	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.490s	1.020ms	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.660s	46.655us	20	20	100.00
		gpio_same_csr_outstanding	0.910s	83.816us	20	20	100.00
		gpio_csr_aliasing	0.900s	31.914us	5	5	100.00
		gpio_csr_hw_reset	0.700s	22.403us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.660s	46.655us	20	20	100.00
		gpio_same_csr_outstanding	0.910s	83.816us	20	20	100.00
		gpio_csr_aliasing	0.900s	31.914us	5	5	100.00
		gpio_csr_hw_reset	0.700s	22.403us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.530s	127.370us	20	20	100.00
		gpio_sec_cm	0.890s	242.640us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.530s	127.370us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	37.158m	203.623ms	20	50	40.00
V3		TOTAL			20	50	40.00
		TOTAL			940	970	96.91

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:827) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 30 failures:
  • Test gpio_stress_all_with_rand_reset has 30 failures.

    • 0.gpio_stress_all_with_rand_reset.110404078227754606465398554891082572082724179828498154996968536486611007089303
      Line 4130, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 69741619913 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 69741619913 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.gpio_stress_all_with_rand_reset.96762777708037177024734536301484024837976099625318978750986086180315447281946
      Line 575, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1027262148 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1027262148 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 28 more failures.

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