GPIO Simulation Results

Tuesday March 19 2024 19:02:40 UTC

GitHub Revision: f7fc348358

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 93166527750821992054916907919379261408154533955814283538537589225972237641118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.570s	59.188us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.500s	56.537us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.580s	80.723us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.650s	109.412us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.680s	17.874us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.650s	50.198us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.550s	253.659us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.890s	33.561us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.470s	156.033us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.650s	50.198us	20	20	100.00
		gpio_csr_aliasing	0.890s	33.561us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.510s	115.018us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.390s	69.362us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.990s	144.067us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.460s	205.316us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	4.010s	128.197us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.860s	200.015us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.620s	538.729us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.460s	2.743ms	50	50	100.00
V2	full_random	gpio_full_random	1.280s	1.595ms	50	50	100.00
V2	stress_all	gpio_stress_all	3.589m	38.429ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.610s	30.549us	50	50	100.00
V2	intr_test	gpio_intr_test	0.670s	12.092us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.410s	1.522ms	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.410s	1.522ms	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.650s	50.198us	20	20	100.00
		gpio_same_csr_outstanding	0.950s	41.469us	20	20	100.00
		gpio_csr_aliasing	0.890s	33.561us	5	5	100.00
		gpio_csr_hw_reset	0.680s	17.874us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.650s	50.198us	20	20	100.00
		gpio_same_csr_outstanding	0.950s	41.469us	20	20	100.00
		gpio_csr_aliasing	0.890s	33.561us	5	5	100.00
		gpio_csr_hw_reset	0.680s	17.874us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.530s	175.473us	20	20	100.00
		gpio_sec_cm	1.010s	164.677us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.530s	175.473us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	51.243m	670.848ms	18	50	36.00
V3		TOTAL			18	50	36.00
		TOTAL			938	970	96.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:827) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 32 failures:
  • Test gpio_stress_all_with_rand_reset has 32 failures.

    • 1.gpio_stress_all_with_rand_reset.39639238390636795424520003597929428965240465800236520932854531775575256734849
      Line 1353, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 80705039449 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 80705039449 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.gpio_stress_all_with_rand_reset.3879605835125858344402199637388650230205933567531297961750335652170878196875
      Line 14839, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 114908120989 ps: (cip_base_vseq.sv:827) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 114908120989 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 30 more failures.

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