GPIO Simulation Results

Thursday March 21 2024 19:02:46 UTC

GitHub Revision: e3ca274e77

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 110450978848188291656921294920309436568649534904994074551053469482156204817270

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.510s	398.131us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.530s	88.208us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.620s	194.958us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.600s	97.022us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.710s	68.673us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.660s	12.043us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.610s	1.490ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.900s	114.631us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.540s	34.364us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.660s	12.043us	20	20	100.00
		gpio_csr_aliasing	0.900s	114.631us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.470s	76.850us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.320s	310.506us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.010s	46.338us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.560s	150.045us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.660s	124.327us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.940s	97.454us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.010s	1.084ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.370s	536.127us	50	50	100.00
V2	full_random	gpio_full_random	1.140s	101.385us	50	50	100.00
V2	stress_all	gpio_stress_all	3.727m	29.225ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.680s	30.082us	50	50	100.00
V2	intr_test	gpio_intr_test	0.670s	11.382us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.120s	177.109us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.120s	177.109us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.660s	12.043us	20	20	100.00
		gpio_same_csr_outstanding	0.900s	211.944us	20	20	100.00
		gpio_csr_aliasing	0.900s	114.631us	5	5	100.00
		gpio_csr_hw_reset	0.710s	68.673us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.660s	12.043us	20	20	100.00
		gpio_same_csr_outstanding	0.900s	211.944us	20	20	100.00
		gpio_csr_aliasing	0.900s	114.631us	5	5	100.00
		gpio_csr_hw_reset	0.710s	68.673us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.510s	134.679us	20	20	100.00
		gpio_sec_cm	1.030s	641.483us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.510s	134.679us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	41.569m	166.313ms	14	50	28.00
V3		TOTAL			14	50	28.00
		TOTAL			934	970	96.29

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 35 failures:
  • Test gpio_stress_all_with_rand_reset has 35 failures.

    • 0.gpio_stress_all_with_rand_reset.106967893100999883517127719094932832127961893610916039799726837002377037498288
      Line 5570, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 322645307076 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 322645307076 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.gpio_stress_all_with_rand_reset.94645504281279079257379003829314985606238276633711904981969251164557443975993
      Line 3744, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 23193689916 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 23193689916 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 33 more failures.

• UVM_ERROR (cip_base_vseq.sv:753) [gpio_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test gpio_stress_all_with_rand_reset has 1 failures.

    • 33.gpio_stress_all_with_rand_reset.76212512500054841779769181834765949295760475137778695569235212238689363819176
      Line 4540, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/33.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 65371278809 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 65371278809 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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