GPIO Simulation Results

Sunday March 24 2024 19:02:40 UTC

GitHub Revision: 70ad420931

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 56687816123908180356912499273064417112757374299033127319246303583078997854118

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.570s	395.549us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.430s	336.676us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.410s	287.610us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.480s	439.374us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.650s	102.264us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.650s	12.629us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.350s	1.926ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.870s	124.260us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.680s	139.001us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.650s	12.629us	20	20	100.00
		gpio_csr_aliasing	0.870s	124.260us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.360s	65.370us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.390s	267.333us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.990s	49.836us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.570s	135.735us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.660s	116.175us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.550s	330.021us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.190s	1.140ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.520s	1.081ms	50	50	100.00
V2	full_random	gpio_full_random	1.120s	278.282us	50	50	100.00
V2	stress_all	gpio_stress_all	3.926m	64.063ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.650s	60.472us	50	50	100.00
V2	intr_test	gpio_intr_test	0.660s	11.315us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.080s	339.713us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.080s	339.713us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.650s	12.629us	20	20	100.00
		gpio_same_csr_outstanding	0.870s	39.006us	20	20	100.00
		gpio_csr_aliasing	0.870s	124.260us	5	5	100.00
		gpio_csr_hw_reset	0.650s	102.264us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.650s	12.629us	20	20	100.00
		gpio_same_csr_outstanding	0.870s	39.006us	20	20	100.00
		gpio_csr_aliasing	0.870s	124.260us	5	5	100.00
		gpio_csr_hw_reset	0.650s	102.264us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.450s	124.980us	20	20	100.00
		gpio_sec_cm	1.000s	179.583us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.450s	124.980us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	48.384m	502.374ms	29	50	58.00
V3		TOTAL			29	50	58.00
		TOTAL			949	970	97.84

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 21 failures:
  • Test gpio_stress_all_with_rand_reset has 21 failures.

    • 5.gpio_stress_all_with_rand_reset.25692028429942846602796875596062883195059177988516490605735349590312539525565
      Line 476, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/5.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 1750497165 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 1750497165 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 6.gpio_stress_all_with_rand_reset.66176491648571701121547740678500340553014691039385095809517512782770633457945
      Line 934, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/6.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 60300070158 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 60300070158 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 19 more failures.

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