GPIO Simulation Results

Tuesday March 26 2024 19:03:00 UTC

GitHub Revision: b111fbcef3

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 29002153775573720681496722306495080473944791482258036550176866636887326742880

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.490s	199.113us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.460s	143.893us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.460s	114.069us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.490s	318.569us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.720s	21.634us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.670s	49.950us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	2.400s	262.479us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.900s	36.254us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.820s	446.712us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.670s	49.950us	20	20	100.00
		gpio_csr_aliasing	0.900s	36.254us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.330s	128.836us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.300s	79.956us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.940s	70.626us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.480s	102.423us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.250s	1.168ms	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.620s	178.146us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	26.810s	514.140us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	5.850s	393.633us	50	50	100.00
V2	full_random	gpio_full_random	1.150s	107.603us	50	50	100.00
V2	stress_all	gpio_stress_all	3.180m	29.941ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.660s	23.570us	50	50	100.00
V2	intr_test	gpio_intr_test	0.680s	42.441us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.310s	363.262us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.310s	363.262us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.670s	49.950us	20	20	100.00
		gpio_same_csr_outstanding	0.850s	54.299us	20	20	100.00
		gpio_csr_aliasing	0.900s	36.254us	5	5	100.00
		gpio_csr_hw_reset	0.720s	21.634us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.670s	49.950us	20	20	100.00
		gpio_same_csr_outstanding	0.850s	54.299us	20	20	100.00
		gpio_csr_aliasing	0.900s	36.254us	5	5	100.00
		gpio_csr_hw_reset	0.720s	21.634us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.610s	120.178us	20	20	100.00
		gpio_sec_cm	0.980s	175.472us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.610s	120.178us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	43.879m	99.748ms	23	50	46.00
V3		TOTAL			23	50	46.00
		TOTAL			943	970	97.22

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 27 failures:
  • Test gpio_stress_all_with_rand_reset has 27 failures.

    • 0.gpio_stress_all_with_rand_reset.18102094118330019854159769946839387951011259340694798305815514854742916479431
      Line 2734, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 60729426919 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 60729426919 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.gpio_stress_all_with_rand_reset.45279499206477271566571260036388048255240634883944869289286566166443125602753
      Line 2781, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 29003886592 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 29003886592 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 25 more failures.

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