1579f6a912
Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
---|---|---|---|---|---|---|---|
V1 | smoke | gpio_smoke | 1.480s | 416.758us | 50 | 50 | 100.00 |
gpio_smoke_no_pullup_pulldown | 1.500s | 206.086us | 50 | 50 | 100.00 | ||
gpio_smoke_en_cdc_prim | 1.370s | 48.918us | 50 | 50 | 100.00 | ||
gpio_smoke_no_pullup_pulldown_en_cdc_prim | 1.600s | 90.318us | 50 | 50 | 100.00 | ||
V1 | csr_hw_reset | gpio_csr_hw_reset | 0.650s | 248.255us | 5 | 5 | 100.00 |
V1 | csr_rw | gpio_csr_rw | 0.650s | 52.907us | 20 | 20 | 100.00 |
V1 | csr_bit_bash | gpio_csr_bit_bash | 3.220s | 351.337us | 5 | 5 | 100.00 |
V1 | csr_aliasing | gpio_csr_aliasing | 0.830s | 42.905us | 5 | 5 | 100.00 |
V1 | csr_mem_rw_with_rand_reset | gpio_csr_mem_rw_with_rand_reset | 1.780s | 78.050us | 20 | 20 | 100.00 |
V1 | regwen_csr_and_corresponding_lockable_csr | gpio_csr_rw | 0.650s | 52.907us | 20 | 20 | 100.00 |
gpio_csr_aliasing | 0.830s | 42.905us | 5 | 5 | 100.00 | ||
V1 | TOTAL | 255 | 255 | 100.00 | |||
V2 | direct_and_masked_out | gpio_random_dout_din | 1.310s | 118.121us | 50 | 50 | 100.00 |
gpio_random_dout_din_no_pullup_pulldown | 1.380s | 119.053us | 50 | 50 | 100.00 | ||
V2 | out_in_regs_read_write | gpio_dout_din_regs_random_rw | 1.010s | 204.168us | 50 | 50 | 100.00 |
V2 | gpio_interrupt_programming | gpio_intr_rand_pgm | 1.540s | 109.362us | 50 | 50 | 100.00 |
V2 | random_interrupt_trigger | gpio_rand_intr_trigger | 3.540s | 123.403us | 50 | 50 | 100.00 |
V2 | interrupt_and_noise_filter | gpio_intr_with_filter_rand_intr_event | 3.690s | 342.520us | 50 | 50 | 100.00 |
V2 | noise_filter_stress | gpio_filter_stress | 28.110s | 3.586ms | 50 | 50 | 100.00 |
V2 | regs_long_reads_and_writes | gpio_random_long_reg_writes_reg_reads | 5.710s | 360.945us | 50 | 50 | 100.00 |
V2 | full_random | gpio_full_random | 1.150s | 80.988us | 50 | 50 | 100.00 |
V2 | stress_all | gpio_stress_all | 3.751m | 21.367ms | 50 | 50 | 100.00 |
V2 | alert_test | gpio_alert_test | 0.640s | 11.110us | 50 | 50 | 100.00 |
V2 | intr_test | gpio_intr_test | 0.690s | 15.713us | 50 | 50 | 100.00 |
V2 | tl_d_oob_addr_access | gpio_tl_errors | 2.620s | 499.149us | 20 | 20 | 100.00 |
V2 | tl_d_illegal_access | gpio_tl_errors | 2.620s | 499.149us | 20 | 20 | 100.00 |
V2 | tl_d_outstanding_access | gpio_csr_rw | 0.650s | 52.907us | 20 | 20 | 100.00 |
gpio_same_csr_outstanding | 0.980s | 42.385us | 20 | 20 | 100.00 | ||
gpio_csr_aliasing | 0.830s | 42.905us | 5 | 5 | 100.00 | ||
gpio_csr_hw_reset | 0.650s | 248.255us | 5 | 5 | 100.00 | ||
V2 | tl_d_partial_access | gpio_csr_rw | 0.650s | 52.907us | 20 | 20 | 100.00 |
gpio_same_csr_outstanding | 0.980s | 42.385us | 20 | 20 | 100.00 | ||
gpio_csr_aliasing | 0.830s | 42.905us | 5 | 5 | 100.00 | ||
gpio_csr_hw_reset | 0.650s | 248.255us | 5 | 5 | 100.00 | ||
V2 | TOTAL | 640 | 640 | 100.00 | |||
V2S | tl_intg_err | gpio_tl_intg_err | 1.630s | 135.497us | 20 | 20 | 100.00 |
gpio_sec_cm | 0.920s | 177.517us | 5 | 5 | 100.00 | ||
V2S | sec_cm_bus_integrity | gpio_tl_intg_err | 1.630s | 135.497us | 20 | 20 | 100.00 |
V2S | TOTAL | 25 | 25 | 100.00 | |||
V3 | stress_all_with_rand_reset | gpio_stress_all_with_rand_reset | 42.941m | 258.579ms | 20 | 50 | 40.00 |
V3 | TOTAL | 20 | 50 | 40.00 | |||
TOTAL | 940 | 970 | 96.91 |
Items | Total | Written | Passing | Progress |
---|---|---|---|---|
V1 | 9 | 9 | 9 | 100.00 |
V2 | 14 | 14 | 14 | 100.00 |
V2S | 2 | 2 | 2 | 100.00 |
V3 | 1 | 1 | 0 | 0.00 |
SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
---|---|---|---|---|---|---|---|
99.63 | 99.06 | 99.24 | 100.00 | -- | 99.80 | 99.68 | 99.99 |
UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses.
has 30 failures:
0.gpio_stress_all_with_rand_reset.62569282340219143022259594286538677533731356898173065638615025457816948452794
Line 396, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 801532019 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 801532019 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.gpio_stress_all_with_rand_reset.96582321269135329961881817630356271650647472842866789928491434930340145056735
Line 1450, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 7913452155 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
UVM_INFO @ 7913452155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 28 more failures.