GPIO Simulation Results

Sunday May 26 2024 19:04:10 UTC

GitHub Revision: 2cf28c40e5

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 76231542290686940289653487239061276463019235878731279188279352215076078972419

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.730s	213.461us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.540s	209.367us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.490s	93.702us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.640s	429.126us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.650s	17.351us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.680s	33.295us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.540s	379.197us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.920s	74.406us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.860s	40.468us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.680s	33.295us	20	20	100.00
		gpio_csr_aliasing	0.920s	74.406us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.380s	221.315us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.420s	116.304us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.010s	43.687us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.530s	212.089us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.440s	697.298us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	4.020s	227.064us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	26.690s	983.533us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.590s	7.880ms	50	50	100.00
V2	full_random	gpio_full_random	1.150s	90.398us	50	50	100.00
V2	stress_all	gpio_stress_all	3.741m	15.038ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.660s	16.671us	50	50	100.00
V2	intr_test	gpio_intr_test	0.680s	46.181us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.410s	169.077us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.410s	169.077us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.680s	33.295us	20	20	100.00
		gpio_same_csr_outstanding	0.950s	35.059us	20	20	100.00
		gpio_csr_aliasing	0.920s	74.406us	5	5	100.00
		gpio_csr_hw_reset	0.650s	17.351us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.680s	33.295us	20	20	100.00
		gpio_same_csr_outstanding	0.950s	35.059us	20	20	100.00
		gpio_csr_aliasing	0.920s	74.406us	5	5	100.00
		gpio_csr_hw_reset	0.650s	17.351us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.610s	1.255ms	20	20	100.00
		gpio_sec_cm	1.030s	123.419us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.610s	1.255ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	35.637m	76.933ms	30	50	60.00
V3		TOTAL			30	50	60.00
		TOTAL			950	970	97.94

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
  • Test gpio_stress_all_with_rand_reset has 20 failures.

    • 4.gpio_stress_all_with_rand_reset.99371898511016960257033175547984707421113962470165060316114613124697072501382
      Line 1691, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/4.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 8666292322 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 8666292322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 11.gpio_stress_all_with_rand_reset.36118813266937664316081915033559616001211192523653638102920466966493851891490
      Line 2830, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/11.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 38691805922 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 38691805922 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

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