GPIO Simulation Results

Tuesday May 28 2024 19:30:06 UTC

GitHub Revision: 0e5093d709

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 51604449886868634540233838791789448907774502353938218657919214072353062987195

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.580s	205.080us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.470s	91.124us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.530s	57.671us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.520s	758.099us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.680s	111.523us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.700s	16.229us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.350s	384.235us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.810s	16.711us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.860s	40.010us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.700s	16.229us	20	20	100.00
		gpio_csr_aliasing	0.810s	16.711us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.470s	261.091us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.400s	32.027us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.030s	107.055us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.530s	544.777us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.660s	587.297us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	4.170s	121.000us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.720s	3.095ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.540s	561.020us	50	50	100.00
V2	full_random	gpio_full_random	1.170s	368.253us	50	50	100.00
V2	stress_all	gpio_stress_all	4.300m	20.962ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.630s	37.657us	50	50	100.00
V2	intr_test	gpio_intr_test	0.750s	13.781us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	2.680s	50.425us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	2.680s	50.425us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.700s	16.229us	20	20	100.00
		gpio_same_csr_outstanding	1.010s	255.575us	20	20	100.00
		gpio_csr_aliasing	0.810s	16.711us	5	5	100.00
		gpio_csr_hw_reset	0.680s	111.523us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.700s	16.229us	20	20	100.00
		gpio_same_csr_outstanding	1.010s	255.575us	20	20	100.00
		gpio_csr_aliasing	0.810s	16.711us	5	5	100.00
		gpio_csr_hw_reset	0.680s	111.523us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.510s	1.301ms	20	20	100.00
		gpio_sec_cm	0.950s	231.208us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.510s	1.301ms	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	42.271m	126.430ms	21	50	42.00
V3		TOTAL			21	50	42.00
		TOTAL			941	970	97.01

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
  • Test gpio_stress_all_with_rand_reset has 28 failures.

    • 0.gpio_stress_all_with_rand_reset.53334523601566799709125109231030299451967340618273078525072661920774311445072
      Line 1746, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 22668412887 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 22668412887 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 4.gpio_stress_all_with_rand_reset.98052442389816743393931166509827342977136114066068478118151849014120601905758
      Line 1586, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/4.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 66975396700 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 66975396700 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 26 more failures.

• UVM_ERROR (cip_base_vseq.sv:753) [gpio_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items. has 1 failures:
  • Test gpio_stress_all_with_rand_reset has 1 failures.

    • 43.gpio_stress_all_with_rand_reset.10697526992002595719437801859378919410202594947911791071324140329221703158829
      Line 26137, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/43.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 839090172081 ps: (cip_base_vseq.sv:753) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 839090172081 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

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