GPIO Simulation Results

Thursday May 30 2024 19:02:59 UTC

GitHub Revision: 8cb25a6867

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 26638040090898561482658723926798947801831709189350919955228328310045202344042

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.590s	328.890us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.660s	331.298us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.620s	99.031us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.550s	427.385us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.680s	48.353us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.700s	46.590us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.440s	1.545ms	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.890s	31.703us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.400s	112.742us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.700s	46.590us	20	20	100.00
		gpio_csr_aliasing	0.890s	31.703us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.510s	121.723us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.510s	212.936us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	1.010s	45.199us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.520s	200.715us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.910s	124.101us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.780s	168.249us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	26.550s	788.265us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.040s	2.063ms	50	50	100.00
V2	full_random	gpio_full_random	1.100s	315.334us	50	50	100.00
V2	stress_all	gpio_stress_all	3.475m	8.030ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.670s	13.697us	50	50	100.00
V2	intr_test	gpio_intr_test	0.670s	18.806us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.440s	413.952us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.440s	413.952us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.700s	46.590us	20	20	100.00
		gpio_same_csr_outstanding	1.000s	17.367us	20	20	100.00
		gpio_csr_aliasing	0.890s	31.703us	5	5	100.00
		gpio_csr_hw_reset	0.680s	48.353us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.700s	46.590us	20	20	100.00
		gpio_same_csr_outstanding	1.000s	17.367us	20	20	100.00
		gpio_csr_aliasing	0.890s	31.703us	5	5	100.00
		gpio_csr_hw_reset	0.680s	48.353us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.500s	418.377us	20	20	100.00
		gpio_sec_cm	1.030s	340.019us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.500s	418.377us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	38.005m	103.294ms	26	50	52.00
V3		TOTAL			26	50	52.00
		TOTAL			946	970	97.53

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:829) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 24 failures:
  • Test gpio_stress_all_with_rand_reset has 24 failures.

    • 0.gpio_stress_all_with_rand_reset.71996592878911601904690557534613069794681451403435940537073814149677992657683
      Line 9177, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/0.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 102776327526 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 102776327526 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 8.gpio_stress_all_with_rand_reset.100878376855036037540985663105717613943753930446668876996269438683503927994770
      Line 8179, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/8.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 44459752711 ps: (cip_base_vseq.sv:829) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 44459752711 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 22 more failures.

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