GPIO Simulation Results

Sunday June 02 2024 19:02:53 UTC

GitHub Revision: 01a208901a

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 50418669159766293903157726892781832882154091083197082086235277423705989875584

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.570s	98.100us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.510s	103.445us	50	50	100.00
		gpio_smoke_en_cdc_prim	1.450s	342.514us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.580s	80.015us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.640s	14.798us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.660s	13.808us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.240s	388.041us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.880s	47.913us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.670s	37.482us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.660s	13.808us	20	20	100.00
		gpio_csr_aliasing	0.880s	47.913us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.330s	79.059us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.340s	65.811us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.960s	171.259us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.500s	489.187us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.660s	127.474us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	3.980s	182.508us	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	28.460s	827.045us	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.560s	563.780us	50	50	100.00
V2	full_random	gpio_full_random	1.140s	311.749us	50	50	100.00
V2	stress_all	gpio_stress_all	3.947m	21.177ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.620s	32.206us	50	50	100.00
V2	intr_test	gpio_intr_test	0.650s	37.580us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.830s	444.053us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.830s	444.053us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.660s	13.808us	20	20	100.00
		gpio_same_csr_outstanding	0.850s	72.036us	20	20	100.00
		gpio_csr_aliasing	0.880s	47.913us	5	5	100.00
		gpio_csr_hw_reset	0.640s	14.798us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.660s	13.808us	20	20	100.00
		gpio_same_csr_outstanding	0.850s	72.036us	20	20	100.00
		gpio_csr_aliasing	0.880s	47.913us	5	5	100.00
		gpio_csr_hw_reset	0.640s	14.798us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.470s	123.207us	20	20	100.00
		gpio_sec_cm	0.970s	86.257us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.470s	123.207us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	54.918m	207.060ms	22	50	44.00
V3		TOTAL			22	50	44.00
		TOTAL			942	970	97.11

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.97

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 28 failures:
  • Test gpio_stress_all_with_rand_reset has 28 failures.

    • 1.gpio_stress_all_with_rand_reset.44653458984062462179316912867359309805760010508432988721462256723054809409455
      Line 1125, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 6391689632 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 6391689632 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.gpio_stress_all_with_rand_reset.97569741800022949174390531494940592252380948919560189332462312623740351801228
      Line 5533, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 106343292710 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 106343292710 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 26 more failures.

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