GPIO Simulation Results

Tuesday June 04 2024 19:02:20 UTC

GitHub Revision: a182fcef27

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 115716131103921631007013649731972014580281041353363476420230431751664670300928

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	gpio_smoke	1.500s	269.424us	50	50	100.00
		gpio_smoke_no_pullup_pulldown	1.480s	1.239ms	50	50	100.00
		gpio_smoke_en_cdc_prim	1.570s	415.582us	50	50	100.00
		gpio_smoke_no_pullup_pulldown_en_cdc_prim	1.510s	418.473us	50	50	100.00
V1	csr_hw_reset	gpio_csr_hw_reset	0.670s	99.125us	5	5	100.00
V1	csr_rw	gpio_csr_rw	0.640s	24.598us	20	20	100.00
V1	csr_bit_bash	gpio_csr_bit_bash	3.370s	742.507us	5	5	100.00
V1	csr_aliasing	gpio_csr_aliasing	0.820s	87.007us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	gpio_csr_mem_rw_with_rand_reset	1.780s	36.782us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	gpio_csr_rw	0.640s	24.598us	20	20	100.00
		gpio_csr_aliasing	0.820s	87.007us	5	5	100.00
V1		TOTAL			255	255	100.00
V2	direct_and_masked_out	gpio_random_dout_din	1.230s	66.006us	50	50	100.00
		gpio_random_dout_din_no_pullup_pulldown	1.370s	82.657us	50	50	100.00
V2	out_in_regs_read_write	gpio_dout_din_regs_random_rw	0.960s	263.145us	50	50	100.00
V2	gpio_interrupt_programming	gpio_intr_rand_pgm	1.540s	66.853us	50	50	100.00
V2	random_interrupt_trigger	gpio_rand_intr_trigger	3.530s	438.711us	50	50	100.00
V2	interrupt_and_noise_filter	gpio_intr_with_filter_rand_intr_event	4.000s	1.434ms	50	50	100.00
V2	noise_filter_stress	gpio_filter_stress	26.960s	4.504ms	50	50	100.00
V2	regs_long_reads_and_writes	gpio_random_long_reg_writes_reg_reads	6.240s	747.761us	50	50	100.00
V2	full_random	gpio_full_random	1.120s	211.397us	50	50	100.00
V2	stress_all	gpio_stress_all	3.744m	33.726ms	50	50	100.00
V2	alert_test	gpio_alert_test	0.650s	22.894us	50	50	100.00
V2	intr_test	gpio_intr_test	0.710s	13.225us	50	50	100.00
V2	tl_d_oob_addr_access	gpio_tl_errors	3.720s	234.936us	20	20	100.00
V2	tl_d_illegal_access	gpio_tl_errors	3.720s	234.936us	20	20	100.00
V2	tl_d_outstanding_access	gpio_csr_rw	0.640s	24.598us	20	20	100.00
		gpio_same_csr_outstanding	0.920s	143.836us	20	20	100.00
		gpio_csr_aliasing	0.820s	87.007us	5	5	100.00
		gpio_csr_hw_reset	0.670s	99.125us	5	5	100.00
V2	tl_d_partial_access	gpio_csr_rw	0.640s	24.598us	20	20	100.00
		gpio_same_csr_outstanding	0.920s	143.836us	20	20	100.00
		gpio_csr_aliasing	0.820s	87.007us	5	5	100.00
		gpio_csr_hw_reset	0.670s	99.125us	5	5	100.00
V2		TOTAL			640	640	100.00
V2S	tl_intg_err	gpio_tl_intg_err	1.560s	420.781us	20	20	100.00
		gpio_sec_cm	0.920s	320.387us	5	5	100.00
V2S	sec_cm_bus_integrity	gpio_tl_intg_err	1.560s	420.781us	20	20	100.00
V2S		TOTAL			25	25	100.00
V3	stress_all_with_rand_reset	gpio_stress_all_with_rand_reset	40.218m	108.862ms	25	50	50.00
V3		TOTAL			25	50	50.00
		TOTAL			945	970	97.42

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	14	14	14	100.00
V2S	2	2	2	100.00
V3	1	1	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
99.63	99.06	99.24	100.00	--	99.80	99.68	99.99

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:828) [gpio_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 25 failures:
  • Test gpio_stress_all_with_rand_reset has 25 failures.

    • 1.gpio_stress_all_with_rand_reset.90575108469446863495026453697355897256554361600446661435205070839732929214446
      Line 10072, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/1.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 330639619882 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 330639619882 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.gpio_stress_all_with_rand_reset.86105251894274231251668909044097273624025913764091930716454538898459951257647
      Line 1009, in log /container/opentitan-public/scratch/os_regression/gpio-sim-vcs/2.gpio_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 29581440150 ps: (cip_base_vseq.sv:828) [uvm_test_top.env.virtual_sequencer.gpio_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 29581440150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 23 more failures.

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